diff options
| author | 2025-02-25 12:48:02 +0100 | |
|---|---|---|
| committer | 2025-02-25 12:48:02 +0100 | |
| commit | d2cf9de726c4b8b45a4b17f244e5e00f57f88c16 (patch) | |
| tree | ce2e2a8dcd8f07ff69158ab1eb1709bcfc1b8800 /vendor/github.com/tetratelabs/wazero/internal/engine | |
| parent | [docs] Fix swagger operation descriptions (#3830) (diff) | |
| download | gotosocial-d2cf9de726c4b8b45a4b17f244e5e00f57f88c16.tar.xz | |
[chore]: Bump github.com/tetratelabs/wazero from 1.8.2 to 1.9.0 (#3827)
Bumps [github.com/tetratelabs/wazero](https://github.com/tetratelabs/wazero) from 1.8.2 to 1.9.0.
- [Release notes](https://github.com/tetratelabs/wazero/releases)
- [Commits](https://github.com/tetratelabs/wazero/compare/v1.8.2...v1.9.0)
---
updated-dependencies:
- dependency-name: github.com/tetratelabs/wazero
dependency-type: direct:production
update-type: version-update:semver-minor
...
Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
Diffstat (limited to 'vendor/github.com/tetratelabs/wazero/internal/engine')
| -rw-r--r-- | vendor/github.com/tetratelabs/wazero/internal/engine/wazevo/backend/isa/amd64/machine.go | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/vendor/github.com/tetratelabs/wazero/internal/engine/wazevo/backend/isa/amd64/machine.go b/vendor/github.com/tetratelabs/wazero/internal/engine/wazevo/backend/isa/amd64/machine.go index 7c27c92af..fd0d69ca9 100644 --- a/vendor/github.com/tetratelabs/wazero/internal/engine/wazevo/backend/isa/amd64/machine.go +++ b/vendor/github.com/tetratelabs/wazero/internal/engine/wazevo/backend/isa/amd64/machine.go @@ -1918,6 +1918,9 @@ func (m *machine) lowerCall(si *ssa.Instruction) { for i := regalloc.RealReg(0); i < 16; i++ { m.insert(m.allocateInstr().asDefineUninitializedReg(regInfo.RealRegToVReg[xmm0+i])) } + // Since Go 1.24 it may also use DX, which is not reserved for the function call's 3 args. + // https://github.com/golang/go/blob/go1.24.0/src/runtime/memmove_amd64.s#L123 + m.insert(m.allocateInstr().asDefineUninitializedReg(regInfo.RealRegToVReg[rdx])) } if isDirectCall { @@ -1933,6 +1936,7 @@ func (m *machine) lowerCall(si *ssa.Instruction) { for i := regalloc.RealReg(0); i < 16; i++ { m.insert(m.allocateInstr().asNopUseReg(regInfo.RealRegToVReg[xmm0+i])) } + m.insert(m.allocateInstr().asNopUseReg(regInfo.RealRegToVReg[rdx])) } var index int |
