From ecdc8379fa8f9d88faca626e7de748c2afbe4910 Mon Sep 17 00:00:00 2001 From: Daenney Date: Sat, 25 Feb 2023 13:12:40 +0100 Subject: [chore] Update gin to v1.9.0 (#1553) --- .../twitchyliquid64/golang-asm/obj/riscv/list.go | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 vendor/github.com/twitchyliquid64/golang-asm/obj/riscv/list.go (limited to 'vendor/github.com/twitchyliquid64/golang-asm/obj/riscv/list.go') diff --git a/vendor/github.com/twitchyliquid64/golang-asm/obj/riscv/list.go b/vendor/github.com/twitchyliquid64/golang-asm/obj/riscv/list.go new file mode 100644 index 000000000..b73f7041d --- /dev/null +++ b/vendor/github.com/twitchyliquid64/golang-asm/obj/riscv/list.go @@ -0,0 +1,33 @@ +// Copyright 2019 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv + +import ( + "fmt" + + "github.com/twitchyliquid64/golang-asm/obj" +) + +func init() { + obj.RegisterRegister(obj.RBaseRISCV, REG_END, RegName) + obj.RegisterOpcode(obj.ABaseRISCV, Anames) +} + +func RegName(r int) string { + switch { + case r == 0: + return "NONE" + case r == REG_G: + return "g" + case r == REG_SP: + return "SP" + case REG_X0 <= r && r <= REG_X31: + return fmt.Sprintf("X%d", r-REG_X0) + case REG_F0 <= r && r <= REG_F31: + return fmt.Sprintf("F%d", r-REG_F0) + default: + return fmt.Sprintf("Rgok(%d)", r-obj.RBaseRISCV) + } +} -- cgit v1.2.3