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Diffstat (limited to 'vendor/github.com/klauspost/cpuid/v2')
19 files changed, 0 insertions, 3265 deletions
diff --git a/vendor/github.com/klauspost/cpuid/v2/.gitignore b/vendor/github.com/klauspost/cpuid/v2/.gitignore deleted file mode 100644 index daf913b1b..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/.gitignore +++ /dev/null @@ -1,24 +0,0 @@ -# Compiled Object files, Static and Dynamic libs (Shared Objects) -*.o -*.a -*.so - -# Folders -_obj -_test - -# Architecture specific extensions/prefixes -*.[568vq] -[568vq].out - -*.cgo1.go -*.cgo2.c -_cgo_defun.c -_cgo_gotypes.go -_cgo_export.* - -_testmain.go - -*.exe -*.test -*.prof diff --git a/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml b/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml deleted file mode 100644 index 944cc0007..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml +++ /dev/null @@ -1,74 +0,0 @@ -# This is an example goreleaser.yaml file with some sane defaults. -# Make sure to check the documentation at http://goreleaser.com - -builds: - - - id: "cpuid" - binary: cpuid - main: ./cmd/cpuid/main.go - env: - - CGO_ENABLED=0 - flags: - - -ldflags=-s -w - goos: - - aix - - linux - - freebsd - - netbsd - - windows - - darwin - goarch: - - 386 - - amd64 - - arm64 - goarm: - - 7 - -archives: - - - id: cpuid - name_template: "cpuid-{{ .Os }}_{{ .Arch }}_{{ .Version }}" - replacements: - aix: AIX - darwin: OSX - linux: Linux - windows: Windows - 386: i386 - amd64: x86_64 - freebsd: FreeBSD - netbsd: NetBSD - format_overrides: - - goos: windows - format: zip - files: - - LICENSE -checksum: - name_template: 'checksums.txt' -snapshot: - name_template: "{{ .Tag }}-next" -changelog: - sort: asc - filters: - exclude: - - '^doc:' - - '^docs:' - - '^test:' - - '^tests:' - - '^Update\sREADME.md' - -nfpms: - - - file_name_template: "cpuid_package_{{ .Version }}_{{ .Os }}_{{ .Arch }}" - vendor: Klaus Post - homepage: https://github.com/klauspost/cpuid - maintainer: Klaus Post <klauspost@gmail.com> - description: CPUID Tool - license: BSD 3-Clause - formats: - - deb - - rpm - replacements: - darwin: Darwin - linux: Linux - freebsd: FreeBSD - amd64: x86_64 diff --git a/vendor/github.com/klauspost/cpuid/v2/CONTRIBUTING.txt b/vendor/github.com/klauspost/cpuid/v2/CONTRIBUTING.txt deleted file mode 100644 index 2ef4714f7..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/CONTRIBUTING.txt +++ /dev/null @@ -1,35 +0,0 @@ -Developer Certificate of Origin
-Version 1.1
-
-Copyright (C) 2015- Klaus Post & Contributors.
-Email: klauspost@gmail.com
-
-Everyone is permitted to copy and distribute verbatim copies of this
-license document, but changing it is not allowed.
-
-
-Developer's Certificate of Origin 1.1
-
-By making a contribution to this project, I certify that:
-
-(a) The contribution was created in whole or in part by me and I
- have the right to submit it under the open source license
- indicated in the file; or
-
-(b) The contribution is based upon previous work that, to the best
- of my knowledge, is covered under an appropriate open source
- license and I have the right under that license to submit that
- work with modifications, whether created in whole or in part
- by me, under the same open source license (unless I am
- permitted to submit under a different license), as indicated
- in the file; or
-
-(c) The contribution was provided directly to me by some other
- person who certified (a), (b) or (c) and I have not modified
- it.
-
-(d) I understand and agree that this project and the contribution
- are public and that a record of the contribution (including all
- personal information I submit with it, including my sign-off) is
- maintained indefinitely and may be redistributed consistent with
- this project or the open source license(s) involved.
diff --git a/vendor/github.com/klauspost/cpuid/v2/LICENSE b/vendor/github.com/klauspost/cpuid/v2/LICENSE deleted file mode 100644 index 5cec7ee94..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/LICENSE +++ /dev/null @@ -1,22 +0,0 @@ -The MIT License (MIT) - -Copyright (c) 2015 Klaus Post - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - diff --git a/vendor/github.com/klauspost/cpuid/v2/README.md b/vendor/github.com/klauspost/cpuid/v2/README.md deleted file mode 100644 index f06ba51c5..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/README.md +++ /dev/null @@ -1,499 +0,0 @@ -# cpuid -Package cpuid provides information about the CPU running the current program. - -CPU features are detected on startup, and kept for fast access through the life of the application. -Currently x86 / x64 (AMD64/i386) and ARM (ARM64) is supported, and no external C (cgo) code is used, which should make the library very easy to use. - -You can access the CPU information by accessing the shared CPU variable of the cpuid library. - -Package home: https://github.com/klauspost/cpuid - -[](https://pkg.go.dev/github.com/klauspost/cpuid/v2) -[](https://github.com/klauspost/cpuid/actions/workflows/go.yml) - -## installing - -`go get -u github.com/klauspost/cpuid/v2` using modules. -Drop `v2` for others. - -Installing binary: - -`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest` - -Or download binaries from release page: https://github.com/klauspost/cpuid/releases - -### Homebrew - -For macOS/Linux users, you can install via [brew](https://brew.sh/) - -```sh -$ brew install cpuid -``` - -## example - -```Go -package main - -import ( - "fmt" - "strings" - - . "github.com/klauspost/cpuid/v2" -) - -func main() { - // Print basic CPU information: - fmt.Println("Name:", CPU.BrandName) - fmt.Println("PhysicalCores:", CPU.PhysicalCores) - fmt.Println("ThreadsPerCore:", CPU.ThreadsPerCore) - fmt.Println("LogicalCores:", CPU.LogicalCores) - fmt.Println("Family", CPU.Family, "Model:", CPU.Model, "Vendor ID:", CPU.VendorID) - fmt.Println("Features:", strings.Join(CPU.FeatureSet(), ",")) - fmt.Println("Cacheline bytes:", CPU.CacheLine) - fmt.Println("L1 Data Cache:", CPU.Cache.L1D, "bytes") - fmt.Println("L1 Instruction Cache:", CPU.Cache.L1I, "bytes") - fmt.Println("L2 Cache:", CPU.Cache.L2, "bytes") - fmt.Println("L3 Cache:", CPU.Cache.L3, "bytes") - fmt.Println("Frequency", CPU.Hz, "hz") - - // Test if we have these specific features: - if CPU.Supports(SSE, SSE2) { - fmt.Println("We have Streaming SIMD 2 Extensions") - } -} -``` - -Sample output: -``` ->go run main.go -Name: AMD Ryzen 9 3950X 16-Core Processor -PhysicalCores: 16 -ThreadsPerCore: 2 -LogicalCores: 32 -Family 23 Model: 113 Vendor ID: AMD -Features: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CMOV,CX16,F16C,FMA3,HTT,HYPERVISOR,LZCNT,MMX,MMXEXT,NX,POPCNT,RDRAND,RDSEED,RDTSCP,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3 -Cacheline bytes: 64 -L1 Data Cache: 32768 bytes -L1 Instruction Cache: 32768 bytes -L2 Cache: 524288 bytes -L3 Cache: 16777216 bytes -Frequency 0 hz -We have Streaming SIMD 2 Extensions -``` - -# usage - -The `cpuid.CPU` provides access to CPU features. Use `cpuid.CPU.Supports()` to check for CPU features. -A faster `cpuid.CPU.Has()` is provided which will usually be inlined by the gc compiler. - -To test a larger number of features, they can be combined using `f := CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2)`, etc. -This can be using with `cpuid.CPU.HasAll(f)` to quickly test if all features are supported. - -Note that for some cpu/os combinations some features will not be detected. -`amd64` has rather good support and should work reliably on all platforms. - -Note that hypervisors may not pass through all CPU features through to the guest OS, -so even if your host supports a feature it may not be visible on guests. - -## arm64 feature detection - -Not all operating systems provide ARM features directly -and there is no safe way to do so for the rest. - -Currently `arm64/linux` and `arm64/freebsd` should be quite reliable. -`arm64/darwin` adds features expected from the M1 processor, but a lot remains undetected. - -A `DetectARM()` can be used if you are able to control your deployment, -it will detect CPU features, but may crash if the OS doesn't intercept the calls. -A `-cpu.arm` flag for detecting unsafe ARM features can be added. See below. - -Note that currently only features are detected on ARM, -no additional information is currently available. - -## flags - -It is possible to add flags that affects cpu detection. - -For this the `Flags()` command is provided. - -This must be called *before* `flag.Parse()` AND after the flags have been parsed `Detect()` must be called. - -This means that any detection used in `init()` functions will not contain these flags. - -Example: - -```Go -package main - -import ( - "flag" - "fmt" - "strings" - - "github.com/klauspost/cpuid/v2" -) - -func main() { - cpuid.Flags() - flag.Parse() - cpuid.Detect() - - // Test if we have these specific features: - if cpuid.CPU.Supports(cpuid.SSE, cpuid.SSE2) { - fmt.Println("We have Streaming SIMD 2 Extensions") - } -} -``` - -## commandline - -Download as binary from: https://github.com/klauspost/cpuid/releases - -Install from source: - -`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest` - -### Example - -``` -λ cpuid -Name: AMD Ryzen 9 3950X 16-Core Processor -Vendor String: AuthenticAMD -Vendor ID: AMD -PhysicalCores: 16 -Threads Per Core: 2 -Logical Cores: 32 -CPU Family 23 Model: 113 -Features: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CLZERO,CMOV,CMPXCHG8,CPBOOST,CX16,F16C,FMA3,FXSR,FXSROPT,HTT,HYPERVISOR,LAHF,LZCNT,MCAOVERFLOW,MMX,MMXEXT,MOVBE,NX,OSXSAVE,POPCNT,RDRAND,RDSEED,RDTSCP,SCE,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3,SUCCOR,X87,XSAVE -Microarchitecture level: 3 -Cacheline bytes: 64 -L1 Instruction Cache: 32768 bytes -L1 Data Cache: 32768 bytes -L2 Cache: 524288 bytes -L3 Cache: 16777216 bytes - -``` -### JSON Output: - -``` -λ cpuid --json -{ - "BrandName": "AMD Ryzen 9 3950X 16-Core Processor", - "VendorID": 2, - "VendorString": "AuthenticAMD", - "PhysicalCores": 16, - "ThreadsPerCore": 2, - "LogicalCores": 32, - "Family": 23, - "Model": 113, - "CacheLine": 64, - "Hz": 0, - "BoostFreq": 0, - "Cache": { - "L1I": 32768, - "L1D": 32768, - "L2": 524288, - "L3": 16777216 - }, - "SGX": { - "Available": false, - "LaunchControl": false, - "SGX1Supported": false, - "SGX2Supported": false, - "MaxEnclaveSizeNot64": 0, - "MaxEnclaveSize64": 0, - "EPCSections": null - }, - "Features": [ - "ADX", - "AESNI", - "AVX", - "AVX2", - "BMI1", - "BMI2", - "CLMUL", - "CLZERO", - "CMOV", - "CMPXCHG8", - "CPBOOST", - "CX16", - "F16C", - "FMA3", - "FXSR", - "FXSROPT", - "HTT", - "HYPERVISOR", - "LAHF", - "LZCNT", - "MCAOVERFLOW", - "MMX", - "MMXEXT", - "MOVBE", - "NX", - "OSXSAVE", - "POPCNT", - "RDRAND", - "RDSEED", - "RDTSCP", - "SCE", - "SHA", - "SSE", - "SSE2", - "SSE3", - "SSE4", - "SSE42", - "SSE4A", - "SSSE3", - "SUCCOR", - "X87", - "XSAVE" - ], - "X64Level": 3 -} -``` - -### Check CPU microarch level - -``` -λ cpuid --check-level=3 -2022/03/18 17:04:40 AMD Ryzen 9 3950X 16-Core Processor -2022/03/18 17:04:40 Microarchitecture level 3 is supported. Max level is 3. -Exit Code 0 - -λ cpuid --check-level=4 -2022/03/18 17:06:18 AMD Ryzen 9 3950X 16-Core Processor -2022/03/18 17:06:18 Microarchitecture level 4 not supported. Max level is 3. -Exit Code 1 -``` - - -## Available flags - -### x86 & amd64 - -| Feature Flag | Description | -|--------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| ADX | Intel ADX (Multi-Precision Add-Carry Instruction Extensions) | -| AESNI | Advanced Encryption Standard New Instructions | -| AMD3DNOW | AMD 3DNOW | -| AMD3DNOWEXT | AMD 3DNowExt | -| AMXBF16 | Tile computational operations on BFLOAT16 numbers | -| AMXINT8 | Tile computational operations on 8-bit integers | -| AMXFP16 | Tile computational operations on FP16 numbers | -| AMXFP8 | Tile computational operations on FP8 numbers | -| AMXTILE | Tile architecture | -| APX_F | Intel APX | -| AVX | AVX functions | -| AVX10 | If set the Intel AVX10 Converged Vector ISA is supported | -| AVX10_128 | If set indicates that AVX10 128-bit vector support is present | -| AVX10_256 | If set indicates that AVX10 256-bit vector support is present | -| AVX10_512 | If set indicates that AVX10 512-bit vector support is present | -| AVX2 | AVX2 functions | -| AVX512BF16 | AVX-512 BFLOAT16 Instructions | -| AVX512BITALG | AVX-512 Bit Algorithms | -| AVX512BW | AVX-512 Byte and Word Instructions | -| AVX512CD | AVX-512 Conflict Detection Instructions | -| AVX512DQ | AVX-512 Doubleword and Quadword Instructions | -| AVX512ER | AVX-512 Exponential and Reciprocal Instructions | -| AVX512F | AVX-512 Foundation | -| AVX512FP16 | AVX-512 FP16 Instructions | -| AVX512IFMA | AVX-512 Integer Fused Multiply-Add Instructions | -| AVX512PF | AVX-512 Prefetch Instructions | -| AVX512VBMI | AVX-512 Vector Bit Manipulation Instructions | -| AVX512VBMI2 | AVX-512 Vector Bit Manipulation Instructions, Version 2 | -| AVX512VL | AVX-512 Vector Length Extensions | -| AVX512VNNI | AVX-512 Vector Neural Network Instructions | -| AVX512VP2INTERSECT | AVX-512 Intersect for D/Q | -| AVX512VPOPCNTDQ | AVX-512 Vector Population Count Doubleword and Quadword | -| AVXIFMA | AVX-IFMA instructions | -| AVXNECONVERT | AVX-NE-CONVERT instructions | -| AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one | -| AVXVNNI | AVX (VEX encoded) VNNI neural network instructions | -| AVXVNNIINT8 | AVX-VNNI-INT8 instructions | -| AVXVNNIINT16 | AVX-VNNI-INT16 instructions | -| BHI_CTRL | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 | -| BMI1 | Bit Manipulation Instruction Set 1 | -| BMI2 | Bit Manipulation Instruction Set 2 | -| CETIBT | Intel CET Indirect Branch Tracking | -| CETSS | Intel CET Shadow Stack | -| CLDEMOTE | Cache Line Demote | -| CLMUL | Carry-less Multiplication | -| CLZERO | CLZERO instruction supported | -| CMOV | i686 CMOV | -| CMPCCXADD | CMPCCXADD instructions | -| CMPSB_SCADBS_SHORT | Fast short CMPSB and SCASB | -| CMPXCHG8 | CMPXCHG8 instruction | -| CPBOOST | Core Performance Boost | -| CPPC | AMD: Collaborative Processor Performance Control | -| CX16 | CMPXCHG16B Instruction | -| EFER_LMSLE_UNS | AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ | -| ENQCMD | Enqueue Command | -| ERMS | Enhanced REP MOVSB/STOSB | -| F16C | Half-precision floating-point conversion | -| FLUSH_L1D | Flush L1D cache | -| FMA3 | Intel FMA 3. Does not imply AVX. | -| FMA4 | Bulldozer FMA4 functions | -| FP128 | AMD: When set, the internal FP/SIMD execution datapath is 128-bits wide | -| FP256 | AMD: When set, the internal FP/SIMD execution datapath is 256-bits wide | -| FSRM | Fast Short Rep Mov | -| FXSR | FXSAVE, FXRESTOR instructions, CR4 bit 9 | -| FXSROPT | FXSAVE/FXRSTOR optimizations | -| GFNI | Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. | -| HLE | Hardware Lock Elision | -| HRESET | If set CPU supports history reset and the IA32_HRESET_ENABLE MSR | -| HTT | Hyperthreading (enabled) | -| HWA | Hardware assert supported. Indicates support for MSRC001_10 | -| HYBRID_CPU | This part has CPUs of more than one type. | -| HYPERVISOR | This bit has been reserved by Intel & AMD for use by hypervisors | -| IA32_ARCH_CAP | IA32_ARCH_CAPABILITIES MSR (Intel) | -| IA32_CORE_CAP | IA32_CORE_CAPABILITIES MSR | -| IBPB | Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) | -| IBRS | AMD: Indirect Branch Restricted Speculation | -| IBRS_PREFERRED | AMD: IBRS is preferred over software solution | -| IBRS_PROVIDES_SMP | AMD: IBRS provides Same Mode Protection | -| IBS | Instruction Based Sampling (AMD) | -| IBSBRNTRGT | Instruction Based Sampling Feature (AMD) | -| IBSFETCHSAM | Instruction Based Sampling Feature (AMD) | -| IBSFFV | Instruction Based Sampling Feature (AMD) | -| IBSOPCNT | Instruction Based Sampling Feature (AMD) | -| IBSOPCNTEXT | Instruction Based Sampling Feature (AMD) | -| IBSOPSAM | Instruction Based Sampling Feature (AMD) | -| IBSRDWROPCNT | Instruction Based Sampling Feature (AMD) | -| IBSRIPINVALIDCHK | Instruction Based Sampling Feature (AMD) | -| IBS_FETCH_CTLX | AMD: IBS fetch control extended MSR supported | -| IBS_OPDATA4 | AMD: IBS op data 4 MSR supported | -| IBS_OPFUSE | AMD: Indicates support for IbsOpFuse | -| IBS_PREVENTHOST | Disallowing IBS use by the host supported | -| IBS_ZEN4 | Fetch and Op IBS support IBS extensions added with Zen4 | -| IDPRED_CTRL | IPRED_DIS | -| INT_WBINVD | WBINVD/WBNOINVD are interruptible. | -| INVLPGB | NVLPGB and TLBSYNC instruction supported | -| KEYLOCKER | Key locker | -| KEYLOCKERW | Key locker wide | -| LAHF | LAHF/SAHF in long mode | -| LAM | If set, CPU supports Linear Address Masking | -| LBRVIRT | LBR virtualization | -| LZCNT | LZCNT instruction | -| MCAOVERFLOW | MCA overflow recovery support. | -| MCDT_NO | Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. | -| MCOMMIT | MCOMMIT instruction supported | -| MD_CLEAR | VERW clears CPU buffers | -| MMX | standard MMX | -| MMXEXT | SSE integer functions or AMD MMX ext | -| MOVBE | MOVBE instruction (big-endian) | -| MOVDIR64B | Move 64 Bytes as Direct Store | -| MOVDIRI | Move Doubleword as Direct Store | -| MOVSB_ZL | Fast Zero-Length MOVSB | -| MPX | Intel MPX (Memory Protection Extensions) | -| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD | -| MSRIRC | Instruction Retired Counter MSR available | -| MSRLIST | Read/Write List of Model Specific Registers | -| MSR_PAGEFLUSH | Page Flush MSR available | -| NRIPS | Indicates support for NRIP save on VMEXIT | -| NX | NX (No-Execute) bit | -| OSXSAVE | XSAVE enabled by OS | -| PCONFIG | PCONFIG for Intel Multi-Key Total Memory Encryption | -| POPCNT | POPCNT instruction | -| PPIN | AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled | -| PREFETCHI | PREFETCHIT0/1 instructions | -| PSFD | Predictive Store Forward Disable | -| RDPRU | RDPRU instruction supported | -| RDRAND | RDRAND instruction is available | -| RDSEED | RDSEED instruction is available | -| RDTSCP | RDTSCP Instruction | -| RRSBA_CTRL | Restricted RSB Alternate | -| RTM | Restricted Transactional Memory | -| RTM_ALWAYS_ABORT | Indicates that the loaded microcode is forcing RTM abort. | -| SERIALIZE | Serialize Instruction Execution | -| SEV | AMD Secure Encrypted Virtualization supported | -| SEV_64BIT | AMD SEV guest execution only allowed from a 64-bit host | -| SEV_ALTERNATIVE | AMD SEV Alternate Injection supported | -| SEV_DEBUGSWAP | Full debug state swap supported for SEV-ES guests | -| SEV_ES | AMD SEV Encrypted State supported | -| SEV_RESTRICTED | AMD SEV Restricted Injection supported | -| SEV_SNP | AMD SEV Secure Nested Paging supported | -| SGX | Software Guard Extensions | -| SGXLC | Software Guard Extensions Launch Control | -| SHA | Intel SHA Extensions | -| SME | AMD Secure Memory Encryption supported | -| SME_COHERENT | AMD Hardware cache coherency across encryption domains enforced | -| SPEC_CTRL_SSBD | Speculative Store Bypass Disable | -| SRBDS_CTRL | SRBDS mitigation MSR available | -| SSE | SSE functions | -| SSE2 | P4 SSE functions | -| SSE3 | Prescott SSE3 functions | -| SSE4 | Penryn SSE4.1 functions | -| SSE42 | Nehalem SSE4.2 functions | -| SSE4A | AMD Barcelona microarchitecture SSE4a instructions | -| SSSE3 | Conroe SSSE3 functions | -| STIBP | Single Thread Indirect Branch Predictors | -| STIBP_ALWAYSON | AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On | -| STOSB_SHORT | Fast short STOSB | -| SUCCOR | Software uncorrectable error containment and recovery capability. | -| SVM | AMD Secure Virtual Machine | -| SVMDA | Indicates support for the SVM decode assists. | -| SVMFBASID | SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control | -| SVML | AMD SVM lock. Indicates support for SVM-Lock. | -| SVMNP | AMD SVM nested paging | -| SVMPF | SVM pause intercept filter. Indicates support for the pause intercept filter | -| SVMPFT | SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold | -| SYSCALL | System-Call Extension (SCE): SYSCALL and SYSRET instructions. | -| SYSEE | SYSENTER and SYSEXIT instructions | -| TBM | AMD Trailing Bit Manipulation | -| TDX_GUEST | Intel Trust Domain Extensions Guest | -| TLB_FLUSH_NESTED | AMD: Flushing includes all the nested translations for guest translations | -| TME | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. | -| TOPEXT | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. | -| TSCRATEMSR | MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 | -| TSXLDTRK | Intel TSX Suspend Load Address Tracking | -| VAES | Vector AES. AVX(512) versions requires additional checks. | -| VMCBCLEAN | VMCB clean bits. Indicates support for VMCB clean bits. | -| VMPL | AMD VM Permission Levels supported | -| VMSA_REGPROT | AMD VMSA Register Protection supported | -| VMX | Virtual Machine Extensions | -| VPCLMULQDQ | Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. | -| VTE | AMD Virtual Transparent Encryption supported | -| WAITPKG | TPAUSE, UMONITOR, UMWAIT | -| WBNOINVD | Write Back and Do Not Invalidate Cache | -| WRMSRNS | Non-Serializing Write to Model Specific Register | -| X87 | FPU | -| XGETBV1 | Supports XGETBV with ECX = 1 | -| XOP | Bulldozer XOP functions | -| XSAVE | XSAVE, XRESTOR, XSETBV, XGETBV | -| XSAVEC | Supports XSAVEC and the compacted form of XRSTOR. | -| XSAVEOPT | XSAVEOPT available | -| XSAVES | Supports XSAVES/XRSTORS and IA32_XSS | - -# ARM features: - -| Feature Flag | Description | -|--------------|------------------------------------------------------------------| -| AESARM | AES instructions | -| ARMCPUID | Some CPU ID registers readable at user-level | -| ASIMD | Advanced SIMD | -| ASIMDDP | SIMD Dot Product | -| ASIMDHP | Advanced SIMD half-precision floating point | -| ASIMDRDM | Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH) | -| ATOMICS | Large System Extensions (LSE) | -| CRC32 | CRC32/CRC32C instructions | -| DCPOP | Data cache clean to Point of Persistence (DC CVAP) | -| EVTSTRM | Generic timer | -| FCMA | Floatin point complex number addition and multiplication | -| FP | Single-precision and double-precision floating point | -| FPHP | Half-precision floating point | -| GPA | Generic Pointer Authentication | -| JSCVT | Javascript-style double->int convert (FJCVTZS) | -| LRCPC | Weaker release consistency (LDAPR, etc) | -| PMULL | Polynomial Multiply instructions (PMULL/PMULL2) | -| SHA1 | SHA-1 instructions (SHA1C, etc) | -| SHA2 | SHA-2 instructions (SHA256H, etc) | -| SHA3 | SHA-3 instructions (EOR3, RAXI, XAR, BCAX) | -| SHA512 | SHA512 instructions | -| SM3 | SM3 instructions | -| SM4 | SM4 instructions | -| SVE | Scalable Vector Extension | - -# license - -This code is published under an MIT license. See LICENSE file for more information. diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid.go b/vendor/github.com/klauspost/cpuid/v2/cpuid.go deleted file mode 100644 index db99eb62f..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/cpuid.go +++ /dev/null @@ -1,1558 +0,0 @@ -// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. - -// Package cpuid provides information about the CPU running the current program. -// -// CPU features are detected on startup, and kept for fast access through the life of the application. -// Currently x86 / x64 (AMD64) as well as arm64 is supported. -// -// You can access the CPU information by accessing the shared CPU variable of the cpuid library. -// -// Package home: https://github.com/klauspost/cpuid -package cpuid - -import ( - "flag" - "fmt" - "math" - "math/bits" - "os" - "runtime" - "strings" -) - -// AMD refererence: https://www.amd.com/system/files/TechDocs/25481.pdf -// and Processor Programming Reference (PPR) - -// Vendor is a representation of a CPU vendor. -type Vendor int - -const ( - VendorUnknown Vendor = iota - Intel - AMD - VIA - Transmeta - NSC - KVM // Kernel-based Virtual Machine - MSVM // Microsoft Hyper-V or Windows Virtual PC - VMware - XenHVM - Bhyve - Hygon - SiS - RDC - - Ampere - ARM - Broadcom - Cavium - DEC - Fujitsu - Infineon - Motorola - NVIDIA - AMCC - Qualcomm - Marvell - - QEMU - QNX - ACRN - SRE - Apple - - lastVendor -) - -//go:generate stringer -type=FeatureID,Vendor - -// FeatureID is the ID of a specific cpu feature. -type FeatureID int - -const ( - // Keep index -1 as unknown - UNKNOWN = -1 - - // x86 features - ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions) - AESNI // Advanced Encryption Standard New Instructions - AMD3DNOW // AMD 3DNOW - AMD3DNOWEXT // AMD 3DNowExt - AMXBF16 // Tile computational operations on BFLOAT16 numbers - AMXFP16 // Tile computational operations on FP16 numbers - AMXINT8 // Tile computational operations on 8-bit integers - AMXFP8 // Tile computational operations on FP8 numbers - AMXTILE // Tile architecture - APX_F // Intel APX - AVX // AVX functions - AVX10 // If set the Intel AVX10 Converged Vector ISA is supported - AVX10_128 // If set indicates that AVX10 128-bit vector support is present - AVX10_256 // If set indicates that AVX10 256-bit vector support is present - AVX10_512 // If set indicates that AVX10 512-bit vector support is present - AVX2 // AVX2 functions - AVX512BF16 // AVX-512 BFLOAT16 Instructions - AVX512BITALG // AVX-512 Bit Algorithms - AVX512BW // AVX-512 Byte and Word Instructions - AVX512CD // AVX-512 Conflict Detection Instructions - AVX512DQ // AVX-512 Doubleword and Quadword Instructions - AVX512ER // AVX-512 Exponential and Reciprocal Instructions - AVX512F // AVX-512 Foundation - AVX512FP16 // AVX-512 FP16 Instructions - AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions - AVX512PF // AVX-512 Prefetch Instructions - AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions - AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2 - AVX512VL // AVX-512 Vector Length Extensions - AVX512VNNI // AVX-512 Vector Neural Network Instructions - AVX512VP2INTERSECT // AVX-512 Intersect for D/Q - AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword - AVXIFMA // AVX-IFMA instructions - AVXNECONVERT // AVX-NE-CONVERT instructions - AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one - AVXVNNI // AVX (VEX encoded) VNNI neural network instructions - AVXVNNIINT8 // AVX-VNNI-INT8 instructions - AVXVNNIINT16 // AVX-VNNI-INT16 instructions - BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 - BMI1 // Bit Manipulation Instruction Set 1 - BMI2 // Bit Manipulation Instruction Set 2 - CETIBT // Intel CET Indirect Branch Tracking - CETSS // Intel CET Shadow Stack - CLDEMOTE // Cache Line Demote - CLMUL // Carry-less Multiplication - CLZERO // CLZERO instruction supported - CMOV // i686 CMOV - CMPCCXADD // CMPCCXADD instructions - CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB - CMPXCHG8 // CMPXCHG8 instruction - CPBOOST // Core Performance Boost - CPPC // AMD: Collaborative Processor Performance Control - CX16 // CMPXCHG16B Instruction - EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ - ENQCMD // Enqueue Command - ERMS // Enhanced REP MOVSB/STOSB - F16C // Half-precision floating-point conversion - FLUSH_L1D // Flush L1D cache - FMA3 // Intel FMA 3. Does not imply AVX. - FMA4 // Bulldozer FMA4 functions - FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide - FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide - FSRM // Fast Short Rep Mov - FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9 - FXSROPT // FXSAVE/FXRSTOR optimizations - GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. - HLE // Hardware Lock Elision - HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR - HTT // Hyperthreading (enabled) - HWA // Hardware assert supported. Indicates support for MSRC001_10 - HYBRID_CPU // This part has CPUs of more than one type. - HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors - IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel) - IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR - IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) - IBPB_BRTYPE // Indicates that MSR 49h (PRED_CMD) bit 0 (IBPB) flushes all branch type predictions from the CPU branch predictor - IBRS // AMD: Indirect Branch Restricted Speculation - IBRS_PREFERRED // AMD: IBRS is preferred over software solution - IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection - IBS // Instruction Based Sampling (AMD) - IBSBRNTRGT // Instruction Based Sampling Feature (AMD) - IBSFETCHSAM // Instruction Based Sampling Feature (AMD) - IBSFFV // Instruction Based Sampling Feature (AMD) - IBSOPCNT // Instruction Based Sampling Feature (AMD) - IBSOPCNTEXT // Instruction Based Sampling Feature (AMD) - IBSOPSAM // Instruction Based Sampling Feature (AMD) - IBSRDWROPCNT // Instruction Based Sampling Feature (AMD) - IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD) - IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported - IBS_OPDATA4 // AMD: IBS op data 4 MSR supported - IBS_OPFUSE // AMD: Indicates support for IbsOpFuse - IBS_PREVENTHOST // Disallowing IBS use by the host supported - IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4 - IDPRED_CTRL // IPRED_DIS - INT_WBINVD // WBINVD/WBNOINVD are interruptible. - INVLPGB // NVLPGB and TLBSYNC instruction supported - KEYLOCKER // Key locker - KEYLOCKERW // Key locker wide - LAHF // LAHF/SAHF in long mode - LAM // If set, CPU supports Linear Address Masking - LBRVIRT // LBR virtualization - LZCNT // LZCNT instruction - MCAOVERFLOW // MCA overflow recovery support. - MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. - MCOMMIT // MCOMMIT instruction supported - MD_CLEAR // VERW clears CPU buffers - MMX // standard MMX - MMXEXT // SSE integer functions or AMD MMX ext - MOVBE // MOVBE instruction (big-endian) - MOVDIR64B // Move 64 Bytes as Direct Store - MOVDIRI // Move Doubleword as Direct Store - MOVSB_ZL // Fast Zero-Length MOVSB - MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD - MPX // Intel MPX (Memory Protection Extensions) - MSRIRC // Instruction Retired Counter MSR available - MSRLIST // Read/Write List of Model Specific Registers - MSR_PAGEFLUSH // Page Flush MSR available - NRIPS // Indicates support for NRIP save on VMEXIT - NX // NX (No-Execute) bit - OSXSAVE // XSAVE enabled by OS - PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption - POPCNT // POPCNT instruction - PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled - PREFETCHI // PREFETCHIT0/1 instructions - PSFD // Predictive Store Forward Disable - RDPRU // RDPRU instruction supported - RDRAND // RDRAND instruction is available - RDSEED // RDSEED instruction is available - RDTSCP // RDTSCP Instruction - RRSBA_CTRL // Restricted RSB Alternate - RTM // Restricted Transactional Memory - RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort. - SBPB // Indicates support for the Selective Branch Predictor Barrier - SERIALIZE // Serialize Instruction Execution - SEV // AMD Secure Encrypted Virtualization supported - SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host - SEV_ALTERNATIVE // AMD SEV Alternate Injection supported - SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests - SEV_ES // AMD SEV Encrypted State supported - SEV_RESTRICTED // AMD SEV Restricted Injection supported - SEV_SNP // AMD SEV Secure Nested Paging supported - SGX // Software Guard Extensions - SGXLC // Software Guard Extensions Launch Control - SHA // Intel SHA Extensions - SME // AMD Secure Memory Encryption supported - SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced - SPEC_CTRL_SSBD // Speculative Store Bypass Disable - SRBDS_CTRL // SRBDS mitigation MSR available - SRSO_MSR_FIX // Indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO. - SRSO_NO // Indicates the CPU is not subject to the SRSO vulnerability - SRSO_USER_KERNEL_NO // Indicates the CPU is not subject to the SRSO vulnerability across user/kernel boundaries - SSE // SSE functions - SSE2 // P4 SSE functions - SSE3 // Prescott SSE3 functions - SSE4 // Penryn SSE4.1 functions - SSE42 // Nehalem SSE4.2 functions - SSE4A // AMD Barcelona microarchitecture SSE4a instructions - SSSE3 // Conroe SSSE3 functions - STIBP // Single Thread Indirect Branch Predictors - STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On - STOSB_SHORT // Fast short STOSB - SUCCOR // Software uncorrectable error containment and recovery capability. - SVM // AMD Secure Virtual Machine - SVMDA // Indicates support for the SVM decode assists. - SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control - SVML // AMD SVM lock. Indicates support for SVM-Lock. - SVMNP // AMD SVM nested paging - SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter - SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold - SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions. - SYSEE // SYSENTER and SYSEXIT instructions - TBM // AMD Trailing Bit Manipulation - TDX_GUEST // Intel Trust Domain Extensions Guest - TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations - TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. - TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. - TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 - TSXLDTRK // Intel TSX Suspend Load Address Tracking - VAES // Vector AES. AVX(512) versions requires additional checks. - VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits. - VMPL // AMD VM Permission Levels supported - VMSA_REGPROT // AMD VMSA Register Protection supported - VMX // Virtual Machine Extensions - VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. - VTE // AMD Virtual Transparent Encryption supported - WAITPKG // TPAUSE, UMONITOR, UMWAIT - WBNOINVD // Write Back and Do Not Invalidate Cache - WRMSRNS // Non-Serializing Write to Model Specific Register - X87 // FPU - XGETBV1 // Supports XGETBV with ECX = 1 - XOP // Bulldozer XOP functions - XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV - XSAVEC // Supports XSAVEC and the compacted form of XRSTOR. - XSAVEOPT // XSAVEOPT available - XSAVES // Supports XSAVES/XRSTORS and IA32_XSS - - // ARM features: - AESARM // AES instructions - ARMCPUID // Some CPU ID registers readable at user-level - ASIMD // Advanced SIMD - ASIMDDP // SIMD Dot Product - ASIMDHP // Advanced SIMD half-precision floating point - ASIMDRDM // Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH) - ATOMICS // Large System Extensions (LSE) - CRC32 // CRC32/CRC32C instructions - DCPOP // Data cache clean to Point of Persistence (DC CVAP) - EVTSTRM // Generic timer - FCMA // Floatin point complex number addition and multiplication - FP // Single-precision and double-precision floating point - FPHP // Half-precision floating point - GPA // Generic Pointer Authentication - JSCVT // Javascript-style double->int convert (FJCVTZS) - LRCPC // Weaker release consistency (LDAPR, etc) - PMULL // Polynomial Multiply instructions (PMULL/PMULL2) - SHA1 // SHA-1 instructions (SHA1C, etc) - SHA2 // SHA-2 instructions (SHA256H, etc) - SHA3 // SHA-3 instructions (EOR3, RAXI, XAR, BCAX) - SHA512 // SHA512 instructions - SM3 // SM3 instructions - SM4 // SM4 instructions - SVE // Scalable Vector Extension - // Keep it last. It automatically defines the size of []flagSet - lastID - - firstID FeatureID = UNKNOWN + 1 -) - -// CPUInfo contains information about the detected system CPU. -type CPUInfo struct { - BrandName string // Brand name reported by the CPU - VendorID Vendor // Comparable CPU vendor ID - VendorString string // Raw vendor string. - HypervisorVendorID Vendor // Hypervisor vendor - HypervisorVendorString string // Raw hypervisor vendor string - featureSet flagSet // Features of the CPU - PhysicalCores int // Number of physical processor cores in your CPU. Will be 0 if undetectable. - ThreadsPerCore int // Number of threads per physical core. Will be 1 if undetectable. - LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable. - Family int // CPU family number - Model int // CPU model number - Stepping int // CPU stepping info - CacheLine int // Cache line size in bytes. Will be 0 if undetectable. - Hz int64 // Clock speed, if known, 0 otherwise. Will attempt to contain base clock speed. - BoostFreq int64 // Max clock speed, if known, 0 otherwise - Cache struct { - L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected - L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected - L2 int // L2 Cache (per core or shared). Will be -1 if undetected - L3 int // L3 Cache (per core, per ccx or shared). Will be -1 if undetected - } - SGX SGXSupport - AMDMemEncryption AMDMemEncryptionSupport - AVX10Level uint8 - - maxFunc uint32 - maxExFunc uint32 -} - -var cpuid func(op uint32) (eax, ebx, ecx, edx uint32) -var cpuidex func(op, op2 uint32) (eax, ebx, ecx, edx uint32) -var xgetbv func(index uint32) (eax, edx uint32) -var rdtscpAsm func() (eax, ebx, ecx, edx uint32) -var darwinHasAVX512 = func() bool { return false } - -// CPU contains information about the CPU as detected on startup, -// or when Detect last was called. -// -// Use this as the primary entry point to you data. -var CPU CPUInfo - -func init() { - initCPU() - Detect() -} - -// Detect will re-detect current CPU info. -// This will replace the content of the exported CPU variable. -// -// Unless you expect the CPU to change while you are running your program -// you should not need to call this function. -// If you call this, you must ensure that no other goroutine is accessing the -// exported CPU variable. -func Detect() { - // Set defaults - CPU.ThreadsPerCore = 1 - CPU.Cache.L1I = -1 - CPU.Cache.L1D = -1 - CPU.Cache.L2 = -1 - CPU.Cache.L3 = -1 - safe := true - if detectArmFlag != nil { - safe = !*detectArmFlag - } - addInfo(&CPU, safe) - if displayFeats != nil && *displayFeats { - fmt.Println("cpu features:", strings.Join(CPU.FeatureSet(), ",")) - // Exit with non-zero so tests will print value. - os.Exit(1) - } - if disableFlag != nil { - s := strings.Split(*disableFlag, ",") - for _, feat := range s { - feat := ParseFeature(strings.TrimSpace(feat)) - if feat != UNKNOWN { - CPU.featureSet.unset(feat) - } - } - } -} - -// DetectARM will detect ARM64 features. -// This is NOT done automatically since it can potentially crash -// if the OS does not handle the command. -// If in the future this can be done safely this function may not -// do anything. -func DetectARM() { - addInfo(&CPU, false) -} - -var detectArmFlag *bool -var displayFeats *bool -var disableFlag *string - -// Flags will enable flags. -// This must be called *before* flag.Parse AND -// Detect must be called after the flags have been parsed. -// Note that this means that any detection used in init() functions -// will not contain these flags. -func Flags() { - disableFlag = flag.String("cpu.disable", "", "disable cpu features; comma separated list") - displayFeats = flag.Bool("cpu.features", false, "lists cpu features and exits") - detectArmFlag = flag.Bool("cpu.arm", false, "allow ARM features to be detected; can potentially crash") -} - -// Supports returns whether the CPU supports all of the requested features. -func (c CPUInfo) Supports(ids ...FeatureID) bool { - for _, id := range ids { - if !c.featureSet.inSet(id) { - return false - } - } - return true -} - -// Has allows for checking a single feature. -// Should be inlined by the compiler. -func (c *CPUInfo) Has(id FeatureID) bool { - return c.featureSet.inSet(id) -} - -// AnyOf returns whether the CPU supports one or more of the requested features. -func (c CPUInfo) AnyOf(ids ...FeatureID) bool { - for _, id := range ids { - if c.featureSet.inSet(id) { - return true - } - } - return false -} - -// Features contains several features combined for a fast check using -// CpuInfo.HasAll -type Features *flagSet - -// CombineFeatures allows to combine several features for a close to constant time lookup. -func CombineFeatures(ids ...FeatureID) Features { - var v flagSet - for _, id := range ids { - v.set(id) - } - return &v -} - -func (c *CPUInfo) HasAll(f Features) bool { - return c.featureSet.hasSetP(f) -} - -// https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels -var oneOfLevel = CombineFeatures(SYSEE, SYSCALL) -var level1Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2) -var level2Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3) -var level3Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE) -var level4Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL) - -// X64Level returns the microarchitecture level detected on the CPU. -// If features are lacking or non x64 mode, 0 is returned. -// See https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels -func (c CPUInfo) X64Level() int { - if !c.featureSet.hasOneOf(oneOfLevel) { - return 0 - } - if c.featureSet.hasSetP(level4Features) { - return 4 - } - if c.featureSet.hasSetP(level3Features) { - return 3 - } - if c.featureSet.hasSetP(level2Features) { - return 2 - } - if c.featureSet.hasSetP(level1Features) { - return 1 - } - return 0 -} - -// Disable will disable one or several features. -func (c *CPUInfo) Disable(ids ...FeatureID) bool { - for _, id := range ids { - c.featureSet.unset(id) - } - return true -} - -// Enable will disable one or several features even if they were undetected. -// This is of course not recommended for obvious reasons. -func (c *CPUInfo) Enable(ids ...FeatureID) bool { - for _, id := range ids { - c.featureSet.set(id) - } - return true -} - -// IsVendor returns true if vendor is recognized as Intel -func (c CPUInfo) IsVendor(v Vendor) bool { - return c.VendorID == v -} - -// FeatureSet returns all available features as strings. -func (c CPUInfo) FeatureSet() []string { - s := make([]string, 0, c.featureSet.nEnabled()) - s = append(s, c.featureSet.Strings()...) - return s -} - -// RTCounter returns the 64-bit time-stamp counter -// Uses the RDTSCP instruction. The value 0 is returned -// if the CPU does not support the instruction. -func (c CPUInfo) RTCounter() uint64 { - if !c.Has(RDTSCP) { - return 0 - } - a, _, _, d := rdtscpAsm() - return uint64(a) | (uint64(d) << 32) -} - -// Ia32TscAux returns the IA32_TSC_AUX part of the RDTSCP. -// This variable is OS dependent, but on Linux contains information -// about the current cpu/core the code is running on. -// If the RDTSCP instruction isn't supported on the CPU, the value 0 is returned. -func (c CPUInfo) Ia32TscAux() uint32 { - if !c.Has(RDTSCP) { - return 0 - } - _, _, ecx, _ := rdtscpAsm() - return ecx -} - -// SveLengths returns arm SVE vector and predicate lengths. -// Will return 0, 0 if SVE is not enabled or otherwise unable to detect. -func (c CPUInfo) SveLengths() (vl, pl uint64) { - if !c.Has(SVE) { - return 0, 0 - } - return getVectorLength() -} - -// LogicalCPU will return the Logical CPU the code is currently executing on. -// This is likely to change when the OS re-schedules the running thread -// to another CPU. -// If the current core cannot be detected, -1 will be returned. -func (c CPUInfo) LogicalCPU() int { - if c.maxFunc < 1 { - return -1 - } - _, ebx, _, _ := cpuid(1) - return int(ebx >> 24) -} - -// frequencies tries to compute the clock speed of the CPU. If leaf 15 is -// supported, use it, otherwise parse the brand string. Yes, really. -func (c *CPUInfo) frequencies() { - c.Hz, c.BoostFreq = 0, 0 - mfi := maxFunctionID() - if mfi >= 0x15 { - eax, ebx, ecx, _ := cpuid(0x15) - if eax != 0 && ebx != 0 && ecx != 0 { - c.Hz = (int64(ecx) * int64(ebx)) / int64(eax) - } - } - if mfi >= 0x16 { - a, b, _, _ := cpuid(0x16) - // Base... - if a&0xffff > 0 { - c.Hz = int64(a&0xffff) * 1_000_000 - } - // Boost... - if b&0xffff > 0 { - c.BoostFreq = int64(b&0xffff) * 1_000_000 - } - } - if c.Hz > 0 { - return - } - - // computeHz determines the official rated speed of a CPU from its brand - // string. This insanity is *actually the official documented way to do - // this according to Intel*, prior to leaf 0x15 existing. The official - // documentation only shows this working for exactly `x.xx` or `xxxx` - // cases, e.g., `2.50GHz` or `1300MHz`; this parser will accept other - // sizes. - model := c.BrandName - hz := strings.LastIndex(model, "Hz") - if hz < 3 { - return - } - var multiplier int64 - switch model[hz-1] { - case 'M': - multiplier = 1000 * 1000 - case 'G': - multiplier = 1000 * 1000 * 1000 - case 'T': - multiplier = 1000 * 1000 * 1000 * 1000 - } - if multiplier == 0 { - return - } - freq := int64(0) - divisor := int64(0) - decimalShift := int64(1) - var i int - for i = hz - 2; i >= 0 && model[i] != ' '; i-- { - if model[i] >= '0' && model[i] <= '9' { - freq += int64(model[i]-'0') * decimalShift - decimalShift *= 10 - } else if model[i] == '.' { - if divisor != 0 { - return - } - divisor = decimalShift - } else { - return - } - } - // we didn't find a space - if i < 0 { - return - } - if divisor != 0 { - c.Hz = (freq * multiplier) / divisor - return - } - c.Hz = freq * multiplier -} - -// VM Will return true if the cpu id indicates we are in -// a virtual machine. -func (c CPUInfo) VM() bool { - return CPU.featureSet.inSet(HYPERVISOR) -} - -// flags contains detected cpu features and characteristics -type flags uint64 - -// log2(bits_in_uint64) -const flagBitsLog2 = 6 -const flagBits = 1 << flagBitsLog2 -const flagMask = flagBits - 1 - -// flagSet contains detected cpu features and characteristics in an array of flags -type flagSet [(lastID + flagMask) / flagBits]flags - -func (s *flagSet) inSet(feat FeatureID) bool { - return s[feat>>flagBitsLog2]&(1<<(feat&flagMask)) != 0 -} - -func (s *flagSet) set(feat FeatureID) { - s[feat>>flagBitsLog2] |= 1 << (feat & flagMask) -} - -// setIf will set a feature if boolean is true. -func (s *flagSet) setIf(cond bool, features ...FeatureID) { - if cond { - for _, offset := range features { - s[offset>>flagBitsLog2] |= 1 << (offset & flagMask) - } - } -} - -func (s *flagSet) unset(offset FeatureID) { - bit := flags(1 << (offset & flagMask)) - s[offset>>flagBitsLog2] = s[offset>>flagBitsLog2] & ^bit -} - -// or with another flagset. -func (s *flagSet) or(other flagSet) { - for i, v := range other[:] { - s[i] |= v - } -} - -// hasSet returns whether all features are present. -func (s *flagSet) hasSet(other flagSet) bool { - for i, v := range other[:] { - if s[i]&v != v { - return false - } - } - return true -} - -// hasSet returns whether all features are present. -func (s *flagSet) hasSetP(other *flagSet) bool { - for i, v := range other[:] { - if s[i]&v != v { - return false - } - } - return true -} - -// hasOneOf returns whether one or more features are present. -func (s *flagSet) hasOneOf(other *flagSet) bool { - for i, v := range other[:] { - if s[i]&v != 0 { - return true - } - } - return false -} - -// nEnabled will return the number of enabled flags. -func (s *flagSet) nEnabled() (n int) { - for _, v := range s[:] { - n += bits.OnesCount64(uint64(v)) - } - return n -} - -func flagSetWith(feat ...FeatureID) flagSet { - var res flagSet - for _, f := range feat { - res.set(f) - } - return res -} - -// ParseFeature will parse the string and return the ID of the matching feature. -// Will return UNKNOWN if not found. -func ParseFeature(s string) FeatureID { - s = strings.ToUpper(s) - for i := firstID; i < lastID; i++ { - if i.String() == s { - return i - } - } - return UNKNOWN -} - -// Strings returns an array of the detected features for FlagsSet. -func (s flagSet) Strings() []string { - if len(s) == 0 { - return []string{""} - } - r := make([]string, 0) - for i := firstID; i < lastID; i++ { - if s.inSet(i) { - r = append(r, i.String()) - } - } - return r -} - -func maxExtendedFunction() uint32 { - eax, _, _, _ := cpuid(0x80000000) - return eax -} - -func maxFunctionID() uint32 { - a, _, _, _ := cpuid(0) - return a -} - -func brandName() string { - if maxExtendedFunction() >= 0x80000004 { - v := make([]uint32, 0, 48) - for i := uint32(0); i < 3; i++ { - a, b, c, d := cpuid(0x80000002 + i) - v = append(v, a, b, c, d) - } - return strings.Trim(string(valAsString(v...)), " ") - } - return "unknown" -} - -func threadsPerCore() int { - mfi := maxFunctionID() - vend, _ := vendorID() - - if mfi < 0x4 || (vend != Intel && vend != AMD) { - return 1 - } - - if mfi < 0xb { - if vend != Intel { - return 1 - } - _, b, _, d := cpuid(1) - if (d & (1 << 28)) != 0 { - // v will contain logical core count - v := (b >> 16) & 255 - if v > 1 { - a4, _, _, _ := cpuid(4) - // physical cores - v2 := (a4 >> 26) + 1 - if v2 > 0 { - return int(v) / int(v2) - } - } - } - return 1 - } - _, b, _, _ := cpuidex(0xb, 0) - if b&0xffff == 0 { - if vend == AMD { - // if >= Zen 2 0x8000001e EBX 15-8 bits means threads per core. - // The number of threads per core is ThreadsPerCore+1 - // See PPR for AMD Family 17h Models 00h-0Fh (page 82) - fam, _, _ := familyModel() - _, _, _, d := cpuid(1) - if (d&(1<<28)) != 0 && fam >= 23 { - if maxExtendedFunction() >= 0x8000001e { - _, b, _, _ := cpuid(0x8000001e) - return int((b>>8)&0xff) + 1 - } - return 2 - } - } - return 1 - } - return int(b & 0xffff) -} - -func logicalCores() int { - mfi := maxFunctionID() - v, _ := vendorID() - switch v { - case Intel: - // Use this on old Intel processors - if mfi < 0xb { - if mfi < 1 { - return 0 - } - // CPUID.1:EBX[23:16] represents the maximum number of addressable IDs (initial APIC ID) - // that can be assigned to logical processors in a physical package. - // The value may not be the same as the number of logical processors that are present in the hardware of a physical package. - _, ebx, _, _ := cpuid(1) - logical := (ebx >> 16) & 0xff - return int(logical) - } - _, b, _, _ := cpuidex(0xb, 1) - return int(b & 0xffff) - case AMD, Hygon: - _, b, _, _ := cpuid(1) - return int((b >> 16) & 0xff) - default: - return 0 - } -} - -func familyModel() (family, model, stepping int) { - if maxFunctionID() < 0x1 { - return 0, 0, 0 - } - eax, _, _, _ := cpuid(1) - // If BaseFamily[3:0] is less than Fh then ExtendedFamily[7:0] is reserved and Family is equal to BaseFamily[3:0]. - family = int((eax >> 8) & 0xf) - extFam := family == 0x6 // Intel is 0x6, needs extended model. - if family == 0xf { - // Add ExtFamily - family += int((eax >> 20) & 0xff) - extFam = true - } - // If BaseFamily[3:0] is less than 0Fh then ExtendedModel[3:0] is reserved and Model is equal to BaseModel[3:0]. - model = int((eax >> 4) & 0xf) - if extFam { - // Add ExtModel - model += int((eax >> 12) & 0xf0) - } - stepping = int(eax & 0xf) - return family, model, stepping -} - -func physicalCores() int { - v, _ := vendorID() - switch v { - case Intel: - return logicalCores() / threadsPerCore() - case AMD, Hygon: - lc := logicalCores() - tpc := threadsPerCore() - if lc > 0 && tpc > 0 { - return lc / tpc - } - - // The following is inaccurate on AMD EPYC 7742 64-Core Processor - if maxExtendedFunction() >= 0x80000008 { - _, _, c, _ := cpuid(0x80000008) - if c&0xff > 0 { - return int(c&0xff) + 1 - } - } - } - return 0 -} - -// Except from http://en.wikipedia.org/wiki/CPUID#EAX.3D0:_Get_vendor_ID -var vendorMapping = map[string]Vendor{ - "AMDisbetter!": AMD, - "AuthenticAMD": AMD, - "CentaurHauls": VIA, - "GenuineIntel": Intel, - "TransmetaCPU": Transmeta, - "GenuineTMx86": Transmeta, - "Geode by NSC": NSC, - "VIA VIA VIA ": VIA, - "KVMKVMKVM": KVM, - "Linux KVM Hv": KVM, - "TCGTCGTCGTCG": QEMU, - "Microsoft Hv": MSVM, - "VMwareVMware": VMware, - "XenVMMXenVMM": XenHVM, - "bhyve bhyve ": Bhyve, - "HygonGenuine": Hygon, - "Vortex86 SoC": SiS, - "SiS SiS SiS ": SiS, - "RiseRiseRise": SiS, - "Genuine RDC": RDC, - "QNXQVMBSQG": QNX, - "ACRNACRNACRN": ACRN, - "SRESRESRESRE": SRE, - "Apple VZ": Apple, -} - -func vendorID() (Vendor, string) { - _, b, c, d := cpuid(0) - v := string(valAsString(b, d, c)) - vend, ok := vendorMapping[v] - if !ok { - return VendorUnknown, v - } - return vend, v -} - -func hypervisorVendorID() (Vendor, string) { - // https://lwn.net/Articles/301888/ - _, b, c, d := cpuid(0x40000000) - v := string(valAsString(b, c, d)) - vend, ok := vendorMapping[v] - if !ok { - return VendorUnknown, v - } - return vend, v -} - -func cacheLine() int { - if maxFunctionID() < 0x1 { - return 0 - } - - _, ebx, _, _ := cpuid(1) - cache := (ebx & 0xff00) >> 5 // cflush size - if cache == 0 && maxExtendedFunction() >= 0x80000006 { - _, _, ecx, _ := cpuid(0x80000006) - cache = ecx & 0xff // cacheline size - } - // TODO: Read from Cache and TLB Information - return int(cache) -} - -func (c *CPUInfo) cacheSize() { - c.Cache.L1D = -1 - c.Cache.L1I = -1 - c.Cache.L2 = -1 - c.Cache.L3 = -1 - vendor, _ := vendorID() - switch vendor { - case Intel: - if maxFunctionID() < 4 { - return - } - c.Cache.L1I, c.Cache.L1D, c.Cache.L2, c.Cache.L3 = 0, 0, 0, 0 - for i := uint32(0); ; i++ { - eax, ebx, ecx, _ := cpuidex(4, i) - cacheType := eax & 15 - if cacheType == 0 { - break - } - cacheLevel := (eax >> 5) & 7 - coherency := int(ebx&0xfff) + 1 - partitions := int((ebx>>12)&0x3ff) + 1 - associativity := int((ebx>>22)&0x3ff) + 1 - sets := int(ecx) + 1 - size := associativity * partitions * coherency * sets - switch cacheLevel { - case 1: - if cacheType == 1 { - // 1 = Data Cache - c.Cache.L1D = size - } else if cacheType == 2 { - // 2 = Instruction Cache - c.Cache.L1I = size - } else { - if c.Cache.L1D < 0 { - c.Cache.L1I = size - } - if c.Cache.L1I < 0 { - c.Cache.L1I = size - } - } - case 2: - c.Cache.L2 = size - case 3: - c.Cache.L3 = size - } - } - case AMD, Hygon: - // Untested. - if maxExtendedFunction() < 0x80000005 { - return - } - _, _, ecx, edx := cpuid(0x80000005) - c.Cache.L1D = int(((ecx >> 24) & 0xFF) * 1024) - c.Cache.L1I = int(((edx >> 24) & 0xFF) * 1024) - - if maxExtendedFunction() < 0x80000006 { - return - } - _, _, ecx, _ = cpuid(0x80000006) - c.Cache.L2 = int(((ecx >> 16) & 0xFFFF) * 1024) - - // CPUID Fn8000_001D_EAX_x[N:0] Cache Properties - if maxExtendedFunction() < 0x8000001D || !c.Has(TOPEXT) { - return - } - - // Xen Hypervisor is buggy and returns the same entry no matter ECX value. - // Hack: When we encounter the same entry 100 times we break. - nSame := 0 - var last uint32 - for i := uint32(0); i < math.MaxUint32; i++ { - eax, ebx, ecx, _ := cpuidex(0x8000001D, i) - - level := (eax >> 5) & 7 - cacheNumSets := ecx + 1 - cacheLineSize := 1 + (ebx & 2047) - cachePhysPartitions := 1 + ((ebx >> 12) & 511) - cacheNumWays := 1 + ((ebx >> 22) & 511) - - typ := eax & 15 - size := int(cacheNumSets * cacheLineSize * cachePhysPartitions * cacheNumWays) - if typ == 0 { - return - } - - // Check for the same value repeated. - comb := eax ^ ebx ^ ecx - if comb == last { - nSame++ - if nSame == 100 { - return - } - } - last = comb - - switch level { - case 1: - switch typ { - case 1: - // Data cache - c.Cache.L1D = size - case 2: - // Inst cache - c.Cache.L1I = size - default: - if c.Cache.L1D < 0 { - c.Cache.L1I = size - } - if c.Cache.L1I < 0 { - c.Cache.L1I = size - } - } - case 2: - c.Cache.L2 = size - case 3: - c.Cache.L3 = size - } - } - } -} - -type SGXEPCSection struct { - BaseAddress uint64 - EPCSize uint64 -} - -type SGXSupport struct { - Available bool - LaunchControl bool - SGX1Supported bool - SGX2Supported bool - MaxEnclaveSizeNot64 int64 - MaxEnclaveSize64 int64 - EPCSections []SGXEPCSection -} - -func hasSGX(available, lc bool) (rval SGXSupport) { - rval.Available = available - - if !available { - return - } - - rval.LaunchControl = lc - - a, _, _, d := cpuidex(0x12, 0) - rval.SGX1Supported = a&0x01 != 0 - rval.SGX2Supported = a&0x02 != 0 - rval.MaxEnclaveSizeNot64 = 1 << (d & 0xFF) // pow 2 - rval.MaxEnclaveSize64 = 1 << ((d >> 8) & 0xFF) // pow 2 - rval.EPCSections = make([]SGXEPCSection, 0) - - for subleaf := uint32(2); subleaf < 2+8; subleaf++ { - eax, ebx, ecx, edx := cpuidex(0x12, subleaf) - leafType := eax & 0xf - - if leafType == 0 { - // Invalid subleaf, stop iterating - break - } else if leafType == 1 { - // EPC Section subleaf - baseAddress := uint64(eax&0xfffff000) + (uint64(ebx&0x000fffff) << 32) - size := uint64(ecx&0xfffff000) + (uint64(edx&0x000fffff) << 32) - - section := SGXEPCSection{BaseAddress: baseAddress, EPCSize: size} - rval.EPCSections = append(rval.EPCSections, section) - } - } - - return -} - -type AMDMemEncryptionSupport struct { - Available bool - CBitPossition uint32 - NumVMPL uint32 - PhysAddrReduction uint32 - NumEntryptedGuests uint32 - MinSevNoEsAsid uint32 -} - -func hasAMDMemEncryption(available bool) (rval AMDMemEncryptionSupport) { - rval.Available = available - if !available { - return - } - - _, b, c, d := cpuidex(0x8000001f, 0) - - rval.CBitPossition = b & 0x3f - rval.PhysAddrReduction = (b >> 6) & 0x3F - rval.NumVMPL = (b >> 12) & 0xf - rval.NumEntryptedGuests = c - rval.MinSevNoEsAsid = d - - return -} - -func support() flagSet { - var fs flagSet - mfi := maxFunctionID() - vend, _ := vendorID() - if mfi < 0x1 { - return fs - } - family, model, _ := familyModel() - - _, _, c, d := cpuid(1) - fs.setIf((d&(1<<0)) != 0, X87) - fs.setIf((d&(1<<8)) != 0, CMPXCHG8) - fs.setIf((d&(1<<11)) != 0, SYSEE) - fs.setIf((d&(1<<15)) != 0, CMOV) - fs.setIf((d&(1<<23)) != 0, MMX) - fs.setIf((d&(1<<24)) != 0, FXSR) - fs.setIf((d&(1<<25)) != 0, FXSROPT) - fs.setIf((d&(1<<25)) != 0, SSE) - fs.setIf((d&(1<<26)) != 0, SSE2) - fs.setIf((c&1) != 0, SSE3) - fs.setIf((c&(1<<5)) != 0, VMX) - fs.setIf((c&(1<<9)) != 0, SSSE3) - fs.setIf((c&(1<<19)) != 0, SSE4) - fs.setIf((c&(1<<20)) != 0, SSE42) - fs.setIf((c&(1<<25)) != 0, AESNI) - fs.setIf((c&(1<<1)) != 0, CLMUL) - fs.setIf(c&(1<<22) != 0, MOVBE) - fs.setIf(c&(1<<23) != 0, POPCNT) - fs.setIf(c&(1<<30) != 0, RDRAND) - - // This bit has been reserved by Intel & AMD for use by hypervisors, - // and indicates the presence of a hypervisor. - fs.setIf(c&(1<<31) != 0, HYPERVISOR) - fs.setIf(c&(1<<29) != 0, F16C) - fs.setIf(c&(1<<13) != 0, CX16) - - if vend == Intel && (d&(1<<28)) != 0 && mfi >= 4 { - fs.setIf(threadsPerCore() > 1, HTT) - } - if vend == AMD && (d&(1<<28)) != 0 && mfi >= 4 { - fs.setIf(threadsPerCore() > 1, HTT) - } - fs.setIf(c&1<<26 != 0, XSAVE) - fs.setIf(c&1<<27 != 0, OSXSAVE) - // Check XGETBV/XSAVE (26), OXSAVE (27) and AVX (28) bits - const avxCheck = 1<<26 | 1<<27 | 1<<28 - if c&avxCheck == avxCheck { - // Check for OS support - eax, _ := xgetbv(0) - if (eax & 0x6) == 0x6 { - fs.set(AVX) - switch vend { - case Intel: - // Older than Haswell. - fs.setIf(family == 6 && model < 60, AVXSLOW) - case AMD: - // Older than Zen 2 - fs.setIf(family < 23 || (family == 23 && model < 49), AVXSLOW) - } - } - } - // FMA3 can be used with SSE registers, so no OS support is strictly needed. - // fma3 and OSXSAVE needed. - const fma3Check = 1<<12 | 1<<27 - fs.setIf(c&fma3Check == fma3Check, FMA3) - - // Check AVX2, AVX2 requires OS support, but BMI1/2 don't. - if mfi >= 7 { - _, ebx, ecx, edx := cpuidex(7, 0) - if fs.inSet(AVX) && (ebx&0x00000020) != 0 { - fs.set(AVX2) - } - // CPUID.(EAX=7, ECX=0).EBX - if (ebx & 0x00000008) != 0 { - fs.set(BMI1) - fs.setIf((ebx&0x00000100) != 0, BMI2) - } - fs.setIf(ebx&(1<<2) != 0, SGX) - fs.setIf(ebx&(1<<4) != 0, HLE) - fs.setIf(ebx&(1<<9) != 0, ERMS) - fs.setIf(ebx&(1<<11) != 0, RTM) - fs.setIf(ebx&(1<<14) != 0, MPX) - fs.setIf(ebx&(1<<18) != 0, RDSEED) - fs.setIf(ebx&(1<<19) != 0, ADX) - fs.setIf(ebx&(1<<29) != 0, SHA) - - // CPUID.(EAX=7, ECX=0).ECX - fs.setIf(ecx&(1<<5) != 0, WAITPKG) - fs.setIf(ecx&(1<<7) != 0, CETSS) - fs.setIf(ecx&(1<<8) != 0, GFNI) - fs.setIf(ecx&(1<<9) != 0, VAES) - fs.setIf(ecx&(1<<10) != 0, VPCLMULQDQ) - fs.setIf(ecx&(1<<13) != 0, TME) - fs.setIf(ecx&(1<<25) != 0, CLDEMOTE) - fs.setIf(ecx&(1<<23) != 0, KEYLOCKER) - fs.setIf(ecx&(1<<27) != 0, MOVDIRI) - fs.setIf(ecx&(1<<28) != 0, MOVDIR64B) - fs.setIf(ecx&(1<<29) != 0, ENQCMD) - fs.setIf(ecx&(1<<30) != 0, SGXLC) - - // CPUID.(EAX=7, ECX=0).EDX - fs.setIf(edx&(1<<4) != 0, FSRM) - fs.setIf(edx&(1<<9) != 0, SRBDS_CTRL) - fs.setIf(edx&(1<<10) != 0, MD_CLEAR) - fs.setIf(edx&(1<<11) != 0, RTM_ALWAYS_ABORT) - fs.setIf(edx&(1<<14) != 0, SERIALIZE) - fs.setIf(edx&(1<<15) != 0, HYBRID_CPU) - fs.setIf(edx&(1<<16) != 0, TSXLDTRK) - fs.setIf(edx&(1<<18) != 0, PCONFIG) - fs.setIf(edx&(1<<20) != 0, CETIBT) - fs.setIf(edx&(1<<26) != 0, IBPB) - fs.setIf(edx&(1<<27) != 0, STIBP) - fs.setIf(edx&(1<<28) != 0, FLUSH_L1D) - fs.setIf(edx&(1<<29) != 0, IA32_ARCH_CAP) - fs.setIf(edx&(1<<30) != 0, IA32_CORE_CAP) - fs.setIf(edx&(1<<31) != 0, SPEC_CTRL_SSBD) - - // CPUID.(EAX=7, ECX=1).EAX - eax1, _, _, edx1 := cpuidex(7, 1) - fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI) - fs.setIf(eax1&(1<<7) != 0, CMPCCXADD) - fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL) - fs.setIf(eax1&(1<<11) != 0, STOSB_SHORT) - fs.setIf(eax1&(1<<12) != 0, CMPSB_SCADBS_SHORT) - fs.setIf(eax1&(1<<22) != 0, HRESET) - fs.setIf(eax1&(1<<23) != 0, AVXIFMA) - fs.setIf(eax1&(1<<26) != 0, LAM) - - // CPUID.(EAX=7, ECX=1).EDX - fs.setIf(edx1&(1<<4) != 0, AVXVNNIINT8) - fs.setIf(edx1&(1<<5) != 0, AVXNECONVERT) - fs.setIf(edx1&(1<<10) != 0, AVXVNNIINT16) - fs.setIf(edx1&(1<<14) != 0, PREFETCHI) - fs.setIf(edx1&(1<<19) != 0, AVX10) - fs.setIf(edx1&(1<<21) != 0, APX_F) - - // Only detect AVX-512 features if XGETBV is supported - if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) { - // Check for OS support - eax, _ := xgetbv(0) - - // Verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and - // ZMM16-ZMM31 state are enabled by OS) - /// and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS). - hasAVX512 := (eax>>5)&7 == 7 && (eax>>1)&3 == 3 - if runtime.GOOS == "darwin" { - hasAVX512 = fs.inSet(AVX) && darwinHasAVX512() - } - if hasAVX512 { - fs.setIf(ebx&(1<<16) != 0, AVX512F) - fs.setIf(ebx&(1<<17) != 0, AVX512DQ) - fs.setIf(ebx&(1<<21) != 0, AVX512IFMA) - fs.setIf(ebx&(1<<26) != 0, AVX512PF) - fs.setIf(ebx&(1<<27) != 0, AVX512ER) - fs.setIf(ebx&(1<<28) != 0, AVX512CD) - fs.setIf(ebx&(1<<30) != 0, AVX512BW) - fs.setIf(ebx&(1<<31) != 0, AVX512VL) - // ecx - fs.setIf(ecx&(1<<1) != 0, AVX512VBMI) - fs.setIf(ecx&(1<<3) != 0, AMXFP8) - fs.setIf(ecx&(1<<6) != 0, AVX512VBMI2) - fs.setIf(ecx&(1<<11) != 0, AVX512VNNI) - fs.setIf(ecx&(1<<12) != 0, AVX512BITALG) - fs.setIf(ecx&(1<<14) != 0, AVX512VPOPCNTDQ) - // edx - fs.setIf(edx&(1<<8) != 0, AVX512VP2INTERSECT) - fs.setIf(edx&(1<<22) != 0, AMXBF16) - fs.setIf(edx&(1<<23) != 0, AVX512FP16) - fs.setIf(edx&(1<<24) != 0, AMXTILE) - fs.setIf(edx&(1<<25) != 0, AMXINT8) - // eax1 = CPUID.(EAX=7, ECX=1).EAX - fs.setIf(eax1&(1<<5) != 0, AVX512BF16) - fs.setIf(eax1&(1<<19) != 0, WRMSRNS) - fs.setIf(eax1&(1<<21) != 0, AMXFP16) - fs.setIf(eax1&(1<<27) != 0, MSRLIST) - } - } - - // CPUID.(EAX=7, ECX=2) - _, _, _, edx = cpuidex(7, 2) - fs.setIf(edx&(1<<0) != 0, PSFD) - fs.setIf(edx&(1<<1) != 0, IDPRED_CTRL) - fs.setIf(edx&(1<<2) != 0, RRSBA_CTRL) - fs.setIf(edx&(1<<4) != 0, BHI_CTRL) - fs.setIf(edx&(1<<5) != 0, MCDT_NO) - - // Add keylocker features. - if fs.inSet(KEYLOCKER) && mfi >= 0x19 { - _, ebx, _, _ := cpuidex(0x19, 0) - fs.setIf(ebx&5 == 5, KEYLOCKERW) // Bit 0 and 2 (1+4) - } - - // Add AVX10 features. - if fs.inSet(AVX10) && mfi >= 0x24 { - _, ebx, _, _ := cpuidex(0x24, 0) - fs.setIf(ebx&(1<<16) != 0, AVX10_128) - fs.setIf(ebx&(1<<17) != 0, AVX10_256) - fs.setIf(ebx&(1<<18) != 0, AVX10_512) - } - } - - // Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1) - // EAX - // Bit 00: XSAVEOPT is available. - // Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set. - // Bit 02: Supports XGETBV with ECX = 1 if set. - // Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set. - // Bits 31 - 04: Reserved. - // EBX - // Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS. - // ECX - // Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be set to 1 only if ECX[n] is 1. - // EDX? - // Bits 07 - 00: Used for XCR0. Bit 08: PT state. Bit 09: Used for XCR0. Bits 12 - 10: Reserved. Bit 13: HWP state. Bits 31 - 14: Reserved. - if mfi >= 0xd { - if fs.inSet(XSAVE) { - eax, _, _, _ := cpuidex(0xd, 1) - fs.setIf(eax&(1<<0) != 0, XSAVEOPT) - fs.setIf(eax&(1<<1) != 0, XSAVEC) - fs.setIf(eax&(1<<2) != 0, XGETBV1) - fs.setIf(eax&(1<<3) != 0, XSAVES) - } - } - if maxExtendedFunction() >= 0x80000001 { - _, _, c, d := cpuid(0x80000001) - if (c & (1 << 5)) != 0 { - fs.set(LZCNT) - fs.set(POPCNT) - } - // ECX - fs.setIf((c&(1<<0)) != 0, LAHF) - fs.setIf((c&(1<<2)) != 0, SVM) - fs.setIf((c&(1<<6)) != 0, SSE4A) - fs.setIf((c&(1<<10)) != 0, IBS) - fs.setIf((c&(1<<22)) != 0, TOPEXT) - - // EDX - fs.setIf(d&(1<<11) != 0, SYSCALL) - fs.setIf(d&(1<<20) != 0, NX) - fs.setIf(d&(1<<22) != 0, MMXEXT) - fs.setIf(d&(1<<23) != 0, MMX) - fs.setIf(d&(1<<24) != 0, FXSR) - fs.setIf(d&(1<<25) != 0, FXSROPT) - fs.setIf(d&(1<<27) != 0, RDTSCP) - fs.setIf(d&(1<<30) != 0, AMD3DNOWEXT) - fs.setIf(d&(1<<31) != 0, AMD3DNOW) - - /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be - * used unless the OS has AVX support. */ - if fs.inSet(AVX) { - fs.setIf((c&(1<<11)) != 0, XOP) - fs.setIf((c&(1<<16)) != 0, FMA4) - } - - } - if maxExtendedFunction() >= 0x80000007 { - _, b, _, d := cpuid(0x80000007) - fs.setIf((b&(1<<0)) != 0, MCAOVERFLOW) - fs.setIf((b&(1<<1)) != 0, SUCCOR) - fs.setIf((b&(1<<2)) != 0, HWA) - fs.setIf((d&(1<<9)) != 0, CPBOOST) - } - - if maxExtendedFunction() >= 0x80000008 { - _, b, _, _ := cpuid(0x80000008) - fs.setIf(b&(1<<28) != 0, PSFD) - fs.setIf(b&(1<<27) != 0, CPPC) - fs.setIf(b&(1<<24) != 0, SPEC_CTRL_SSBD) - fs.setIf(b&(1<<23) != 0, PPIN) - fs.setIf(b&(1<<21) != 0, TLB_FLUSH_NESTED) - fs.setIf(b&(1<<20) != 0, EFER_LMSLE_UNS) - fs.setIf(b&(1<<19) != 0, IBRS_PROVIDES_SMP) - fs.setIf(b&(1<<18) != 0, IBRS_PREFERRED) - fs.setIf(b&(1<<17) != 0, STIBP_ALWAYSON) - fs.setIf(b&(1<<15) != 0, STIBP) - fs.setIf(b&(1<<14) != 0, IBRS) - fs.setIf((b&(1<<13)) != 0, INT_WBINVD) - fs.setIf(b&(1<<12) != 0, IBPB) - fs.setIf((b&(1<<9)) != 0, WBNOINVD) - fs.setIf((b&(1<<8)) != 0, MCOMMIT) - fs.setIf((b&(1<<4)) != 0, RDPRU) - fs.setIf((b&(1<<3)) != 0, INVLPGB) - fs.setIf((b&(1<<1)) != 0, MSRIRC) - fs.setIf((b&(1<<0)) != 0, CLZERO) - } - - if fs.inSet(SVM) && maxExtendedFunction() >= 0x8000000A { - _, _, _, edx := cpuid(0x8000000A) - fs.setIf((edx>>0)&1 == 1, SVMNP) - fs.setIf((edx>>1)&1 == 1, LBRVIRT) - fs.setIf((edx>>2)&1 == 1, SVML) - fs.setIf((edx>>3)&1 == 1, NRIPS) - fs.setIf((edx>>4)&1 == 1, TSCRATEMSR) - fs.setIf((edx>>5)&1 == 1, VMCBCLEAN) - fs.setIf((edx>>6)&1 == 1, SVMFBASID) - fs.setIf((edx>>7)&1 == 1, SVMDA) - fs.setIf((edx>>10)&1 == 1, SVMPF) - fs.setIf((edx>>12)&1 == 1, SVMPFT) - } - - if maxExtendedFunction() >= 0x8000001a { - eax, _, _, _ := cpuid(0x8000001a) - fs.setIf((eax>>0)&1 == 1, FP128) - fs.setIf((eax>>1)&1 == 1, MOVU) - fs.setIf((eax>>2)&1 == 1, FP256) - } - - if maxExtendedFunction() >= 0x8000001b && fs.inSet(IBS) { - eax, _, _, _ := cpuid(0x8000001b) - fs.setIf((eax>>0)&1 == 1, IBSFFV) - fs.setIf((eax>>1)&1 == 1, IBSFETCHSAM) - fs.setIf((eax>>2)&1 == 1, IBSOPSAM) - fs.setIf((eax>>3)&1 == 1, IBSRDWROPCNT) - fs.setIf((eax>>4)&1 == 1, IBSOPCNT) - fs.setIf((eax>>5)&1 == 1, IBSBRNTRGT) - fs.setIf((eax>>6)&1 == 1, IBSOPCNTEXT) - fs.setIf((eax>>7)&1 == 1, IBSRIPINVALIDCHK) - fs.setIf((eax>>8)&1 == 1, IBS_OPFUSE) - fs.setIf((eax>>9)&1 == 1, IBS_FETCH_CTLX) - fs.setIf((eax>>10)&1 == 1, IBS_OPDATA4) // Doc says "Fixed,0. IBS op data 4 MSR supported", but assuming they mean 1. - fs.setIf((eax>>11)&1 == 1, IBS_ZEN4) - } - - if maxExtendedFunction() >= 0x8000001f && vend == AMD { - a, _, _, _ := cpuid(0x8000001f) - fs.setIf((a>>0)&1 == 1, SME) - fs.setIf((a>>1)&1 == 1, SEV) - fs.setIf((a>>2)&1 == 1, MSR_PAGEFLUSH) - fs.setIf((a>>3)&1 == 1, SEV_ES) - fs.setIf((a>>4)&1 == 1, SEV_SNP) - fs.setIf((a>>5)&1 == 1, VMPL) - fs.setIf((a>>10)&1 == 1, SME_COHERENT) - fs.setIf((a>>11)&1 == 1, SEV_64BIT) - fs.setIf((a>>12)&1 == 1, SEV_RESTRICTED) - fs.setIf((a>>13)&1 == 1, SEV_ALTERNATIVE) - fs.setIf((a>>14)&1 == 1, SEV_DEBUGSWAP) - fs.setIf((a>>15)&1 == 1, IBS_PREVENTHOST) - fs.setIf((a>>16)&1 == 1, VTE) - fs.setIf((a>>24)&1 == 1, VMSA_REGPROT) - } - - if maxExtendedFunction() >= 0x80000021 && vend == AMD { - a, _, _, _ := cpuid(0x80000021) - fs.setIf((a>>31)&1 == 1, SRSO_MSR_FIX) - fs.setIf((a>>30)&1 == 1, SRSO_USER_KERNEL_NO) - fs.setIf((a>>29)&1 == 1, SRSO_NO) - fs.setIf((a>>28)&1 == 1, IBPB_BRTYPE) - fs.setIf((a>>27)&1 == 1, SBPB) - } - - if mfi >= 0x20 { - // Microsoft has decided to purposefully hide the information - // of the guest TEE when VMs are being created using Hyper-V. - // - // This leads us to check for the Hyper-V cpuid features - // (0x4000000C), and then for the `ebx` value set. - // - // For Intel TDX, `ebx` is set as `0xbe3`, being 3 the part - // we're mostly interested about,according to: - // https://github.com/torvalds/linux/blob/d2f51b3516dade79269ff45eae2a7668ae711b25/arch/x86/include/asm/hyperv-tlfs.h#L169-L174 - _, ebx, _, _ := cpuid(0x4000000C) - fs.setIf(ebx == 0xbe3, TDX_GUEST) - } - - if mfi >= 0x21 { - // Intel Trusted Domain Extensions Guests have their own cpuid leaf (0x21). - _, ebx, ecx, edx := cpuid(0x21) - identity := string(valAsString(ebx, edx, ecx)) - fs.setIf(identity == "IntelTDX ", TDX_GUEST) - } - - return fs -} - -func (c *CPUInfo) supportAVX10() uint8 { - if c.maxFunc >= 0x24 && c.featureSet.inSet(AVX10) { - _, ebx, _, _ := cpuidex(0x24, 0) - return uint8(ebx) - } - return 0 -} - -func valAsString(values ...uint32) []byte { - r := make([]byte, 4*len(values)) - for i, v := range values { - dst := r[i*4:] - dst[0] = byte(v & 0xff) - dst[1] = byte((v >> 8) & 0xff) - dst[2] = byte((v >> 16) & 0xff) - dst[3] = byte((v >> 24) & 0xff) - switch { - case dst[0] == 0: - return r[:i*4] - case dst[1] == 0: - return r[:i*4+1] - case dst[2] == 0: - return r[:i*4+2] - case dst[3] == 0: - return r[:i*4+3] - } - } - return r -} diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid_386.s b/vendor/github.com/klauspost/cpuid/v2/cpuid_386.s deleted file mode 100644 index 8587c3a1f..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/cpuid_386.s +++ /dev/null @@ -1,47 +0,0 @@ -// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. - -//+build 386,!gccgo,!noasm,!appengine - -// func asmCpuid(op uint32) (eax, ebx, ecx, edx uint32) -TEXT ·asmCpuid(SB), 7, $0 - XORL CX, CX - MOVL op+0(FP), AX - CPUID - MOVL AX, eax+4(FP) - MOVL BX, ebx+8(FP) - MOVL CX, ecx+12(FP) - MOVL DX, edx+16(FP) - RET - -// func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32) -TEXT ·asmCpuidex(SB), 7, $0 - MOVL op+0(FP), AX - MOVL op2+4(FP), CX - CPUID - MOVL AX, eax+8(FP) - MOVL BX, ebx+12(FP) - MOVL CX, ecx+16(FP) - MOVL DX, edx+20(FP) - RET - -// func xgetbv(index uint32) (eax, edx uint32) -TEXT ·asmXgetbv(SB), 7, $0 - MOVL index+0(FP), CX - BYTE $0x0f; BYTE $0x01; BYTE $0xd0 // XGETBV - MOVL AX, eax+4(FP) - MOVL DX, edx+8(FP) - RET - -// func asmRdtscpAsm() (eax, ebx, ecx, edx uint32) -TEXT ·asmRdtscpAsm(SB), 7, $0 - BYTE $0x0F; BYTE $0x01; BYTE $0xF9 // RDTSCP - MOVL AX, eax+0(FP) - MOVL BX, ebx+4(FP) - MOVL CX, ecx+8(FP) - MOVL DX, edx+12(FP) - RET - -// func asmDarwinHasAVX512() bool -TEXT ·asmDarwinHasAVX512(SB), 7, $0 - MOVL $0, eax+0(FP) - RET diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid_amd64.s b/vendor/github.com/klauspost/cpuid/v2/cpuid_amd64.s deleted file mode 100644 index bc11f8942..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/cpuid_amd64.s +++ /dev/null @@ -1,72 +0,0 @@ -// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. - -//+build amd64,!gccgo,!noasm,!appengine - -// func asmCpuid(op uint32) (eax, ebx, ecx, edx uint32) -TEXT ·asmCpuid(SB), 7, $0 - XORQ CX, CX - MOVL op+0(FP), AX - CPUID - MOVL AX, eax+8(FP) - MOVL BX, ebx+12(FP) - MOVL CX, ecx+16(FP) - MOVL DX, edx+20(FP) - RET - -// func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32) -TEXT ·asmCpuidex(SB), 7, $0 - MOVL op+0(FP), AX - MOVL op2+4(FP), CX - CPUID - MOVL AX, eax+8(FP) - MOVL BX, ebx+12(FP) - MOVL CX, ecx+16(FP) - MOVL DX, edx+20(FP) - RET - -// func asmXgetbv(index uint32) (eax, edx uint32) -TEXT ·asmXgetbv(SB), 7, $0 - MOVL index+0(FP), CX - BYTE $0x0f; BYTE $0x01; BYTE $0xd0 // XGETBV - MOVL AX, eax+8(FP) - MOVL DX, edx+12(FP) - RET - -// func asmRdtscpAsm() (eax, ebx, ecx, edx uint32) -TEXT ·asmRdtscpAsm(SB), 7, $0 - BYTE $0x0F; BYTE $0x01; BYTE $0xF9 // RDTSCP - MOVL AX, eax+0(FP) - MOVL BX, ebx+4(FP) - MOVL CX, ecx+8(FP) - MOVL DX, edx+12(FP) - RET - -// From https://go-review.googlesource.com/c/sys/+/285572/ -// func asmDarwinHasAVX512() bool -TEXT ·asmDarwinHasAVX512(SB), 7, $0-1 - MOVB $0, ret+0(FP) // default to false - -#ifdef GOOS_darwin // return if not darwin -#ifdef GOARCH_amd64 // return if not amd64 -// These values from: -// https://github.com/apple/darwin-xnu/blob/xnu-4570.1.46/osfmk/i386/cpu_capabilities.h -#define commpage64_base_address 0x00007fffffe00000 -#define commpage64_cpu_capabilities64 (commpage64_base_address+0x010) -#define commpage64_version (commpage64_base_address+0x01E) -#define hasAVX512F 0x0000004000000000 - MOVQ $commpage64_version, BX - MOVW (BX), AX - CMPW AX, $13 // versions < 13 do not support AVX512 - JL no_avx512 - MOVQ $commpage64_cpu_capabilities64, BX - MOVQ (BX), AX - MOVQ $hasAVX512F, CX - ANDQ CX, AX - JZ no_avx512 - MOVB $1, ret+0(FP) - -no_avx512: -#endif -#endif - RET - diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s b/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s deleted file mode 100644 index b196f78eb..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s +++ /dev/null @@ -1,36 +0,0 @@ -// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. - -//+build arm64,!gccgo,!noasm,!appengine - -// See https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt - -// func getMidr -TEXT ·getMidr(SB), 7, $0 - WORD $0xd5380000 // mrs x0, midr_el1 /* Main ID Register */ - MOVD R0, midr+0(FP) - RET - -// func getProcFeatures -TEXT ·getProcFeatures(SB), 7, $0 - WORD $0xd5380400 // mrs x0, id_aa64pfr0_el1 /* Processor Feature Register 0 */ - MOVD R0, procFeatures+0(FP) - RET - -// func getInstAttributes -TEXT ·getInstAttributes(SB), 7, $0 - WORD $0xd5380600 // mrs x0, id_aa64isar0_el1 /* Instruction Set Attribute Register 0 */ - WORD $0xd5380621 // mrs x1, id_aa64isar1_el1 /* Instruction Set Attribute Register 1 */ - MOVD R0, instAttrReg0+0(FP) - MOVD R1, instAttrReg1+8(FP) - RET - -TEXT ·getVectorLength(SB), 7, $0 - WORD $0xd2800002 // mov x2, #0 - WORD $0x04225022 // addvl x2, x2, #1 - WORD $0xd37df042 // lsl x2, x2, #3 - WORD $0xd2800003 // mov x3, #0 - WORD $0x04635023 // addpl x3, x3, #1 - WORD $0xd37df063 // lsl x3, x3, #3 - MOVD R2, vl+0(FP) - MOVD R3, pl+8(FP) - RET diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go deleted file mode 100644 index 566743d22..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go +++ /dev/null @@ -1,248 +0,0 @@ -// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. - -//go:build arm64 && !gccgo && !noasm && !appengine -// +build arm64,!gccgo,!noasm,!appengine - -package cpuid - -import "runtime" - -func getMidr() (midr uint64) -func getProcFeatures() (procFeatures uint64) -func getInstAttributes() (instAttrReg0, instAttrReg1 uint64) -func getVectorLength() (vl, pl uint64) - -func initCPU() { - cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } - cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } - xgetbv = func(uint32) (a, b uint32) { return 0, 0 } - rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 } -} - -func addInfo(c *CPUInfo, safe bool) { - // Seems to be safe to assume on ARM64 - c.CacheLine = 64 - detectOS(c) - - // ARM64 disabled since it may crash if interrupt is not intercepted by OS. - if safe && !c.Has(ARMCPUID) && runtime.GOOS != "freebsd" { - return - } - midr := getMidr() - - // MIDR_EL1 - Main ID Register - // https://developer.arm.com/docs/ddi0595/h/aarch64-system-registers/midr_el1 - // x--------------------------------------------------x - // | Name | bits | visible | - // |--------------------------------------------------| - // | Implementer | [31-24] | y | - // |--------------------------------------------------| - // | Variant | [23-20] | y | - // |--------------------------------------------------| - // | Architecture | [19-16] | y | - // |--------------------------------------------------| - // | PartNum | [15-4] | y | - // |--------------------------------------------------| - // | Revision | [3-0] | y | - // x--------------------------------------------------x - - switch (midr >> 24) & 0xff { - case 0xC0: - c.VendorString = "Ampere Computing" - c.VendorID = Ampere - case 0x41: - c.VendorString = "Arm Limited" - c.VendorID = ARM - case 0x42: - c.VendorString = "Broadcom Corporation" - c.VendorID = Broadcom - case 0x43: - c.VendorString = "Cavium Inc" - c.VendorID = Cavium - case 0x44: - c.VendorString = "Digital Equipment Corporation" - c.VendorID = DEC - case 0x46: - c.VendorString = "Fujitsu Ltd" - c.VendorID = Fujitsu - case 0x49: - c.VendorString = "Infineon Technologies AG" - c.VendorID = Infineon - case 0x4D: - c.VendorString = "Motorola or Freescale Semiconductor Inc" - c.VendorID = Motorola - case 0x4E: - c.VendorString = "NVIDIA Corporation" - c.VendorID = NVIDIA - case 0x50: - c.VendorString = "Applied Micro Circuits Corporation" - c.VendorID = AMCC - case 0x51: - c.VendorString = "Qualcomm Inc" - c.VendorID = Qualcomm - case 0x56: - c.VendorString = "Marvell International Ltd" - c.VendorID = Marvell - case 0x69: - c.VendorString = "Intel Corporation" - c.VendorID = Intel - } - - // Lower 4 bits: Architecture - // Architecture Meaning - // 0b0001 Armv4. - // 0b0010 Armv4T. - // 0b0011 Armv5 (obsolete). - // 0b0100 Armv5T. - // 0b0101 Armv5TE. - // 0b0110 Armv5TEJ. - // 0b0111 Armv6. - // 0b1111 Architectural features are individually identified in the ID_* registers, see 'ID registers'. - // Upper 4 bit: Variant - // An IMPLEMENTATION DEFINED variant number. - // Typically, this field is used to distinguish between different product variants, or major revisions of a product. - c.Family = int(midr>>16) & 0xff - - // PartNum, bits [15:4] - // An IMPLEMENTATION DEFINED primary part number for the device. - // On processors implemented by Arm, if the top four bits of the primary - // part number are 0x0 or 0x7, the variant and architecture are encoded differently. - // Revision, bits [3:0] - // An IMPLEMENTATION DEFINED revision number for the device. - c.Model = int(midr) & 0xffff - - procFeatures := getProcFeatures() - - // ID_AA64PFR0_EL1 - Processor Feature Register 0 - // x--------------------------------------------------x - // | Name | bits | visible | - // |--------------------------------------------------| - // | DIT | [51-48] | y | - // |--------------------------------------------------| - // | SVE | [35-32] | y | - // |--------------------------------------------------| - // | GIC | [27-24] | n | - // |--------------------------------------------------| - // | AdvSIMD | [23-20] | y | - // |--------------------------------------------------| - // | FP | [19-16] | y | - // |--------------------------------------------------| - // | EL3 | [15-12] | n | - // |--------------------------------------------------| - // | EL2 | [11-8] | n | - // |--------------------------------------------------| - // | EL1 | [7-4] | n | - // |--------------------------------------------------| - // | EL0 | [3-0] | n | - // x--------------------------------------------------x - - var f flagSet - // if procFeatures&(0xf<<48) != 0 { - // fmt.Println("DIT") - // } - f.setIf(procFeatures&(0xf<<32) != 0, SVE) - if procFeatures&(0xf<<20) != 15<<20 { - f.set(ASIMD) - // https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64pfr0_el1 - // 0b0001 --> As for 0b0000, and also includes support for half-precision floating-point arithmetic. - f.setIf(procFeatures&(0xf<<20) == 1<<20, FPHP, ASIMDHP) - } - f.setIf(procFeatures&(0xf<<16) != 0, FP) - - instAttrReg0, instAttrReg1 := getInstAttributes() - - // https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar0_el1 - // - // ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 - // x--------------------------------------------------x - // | Name | bits | visible | - // |--------------------------------------------------| - // | TS | [55-52] | y | - // |--------------------------------------------------| - // | FHM | [51-48] | y | - // |--------------------------------------------------| - // | DP | [47-44] | y | - // |--------------------------------------------------| - // | SM4 | [43-40] | y | - // |--------------------------------------------------| - // | SM3 | [39-36] | y | - // |--------------------------------------------------| - // | SHA3 | [35-32] | y | - // |--------------------------------------------------| - // | RDM | [31-28] | y | - // |--------------------------------------------------| - // | ATOMICS | [23-20] | y | - // |--------------------------------------------------| - // | CRC32 | [19-16] | y | - // |--------------------------------------------------| - // | SHA2 | [15-12] | y | - // |--------------------------------------------------| - // | SHA1 | [11-8] | y | - // |--------------------------------------------------| - // | AES | [7-4] | y | - // x--------------------------------------------------x - - // if instAttrReg0&(0xf<<52) != 0 { - // fmt.Println("TS") - // } - // if instAttrReg0&(0xf<<48) != 0 { - // fmt.Println("FHM") - // } - f.setIf(instAttrReg0&(0xf<<44) != 0, ASIMDDP) - f.setIf(instAttrReg0&(0xf<<40) != 0, SM4) - f.setIf(instAttrReg0&(0xf<<36) != 0, SM3) - f.setIf(instAttrReg0&(0xf<<32) != 0, SHA3) - f.setIf(instAttrReg0&(0xf<<28) != 0, ASIMDRDM) - f.setIf(instAttrReg0&(0xf<<20) != 0, ATOMICS) - f.setIf(instAttrReg0&(0xf<<16) != 0, CRC32) - f.setIf(instAttrReg0&(0xf<<12) != 0, SHA2) - // https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar0_el1 - // 0b0010 --> As 0b0001, plus SHA512H, SHA512H2, SHA512SU0, and SHA512SU1 instructions implemented. - f.setIf(instAttrReg0&(0xf<<12) == 2<<12, SHA512) - f.setIf(instAttrReg0&(0xf<<8) != 0, SHA1) - f.setIf(instAttrReg0&(0xf<<4) != 0, AESARM) - // https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar0_el1 - // 0b0010 --> As for 0b0001, plus PMULL/PMULL2 instructions operating on 64-bit data quantities. - f.setIf(instAttrReg0&(0xf<<4) == 2<<4, PMULL) - - // https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar1_el1 - // - // ID_AA64ISAR1_EL1 - Instruction set attribute register 1 - // x--------------------------------------------------x - // | Name | bits | visible | - // |--------------------------------------------------| - // | GPI | [31-28] | y | - // |--------------------------------------------------| - // | GPA | [27-24] | y | - // |--------------------------------------------------| - // | LRCPC | [23-20] | y | - // |--------------------------------------------------| - // | FCMA | [19-16] | y | - // |--------------------------------------------------| - // | JSCVT | [15-12] | y | - // |--------------------------------------------------| - // | API | [11-8] | y | - // |--------------------------------------------------| - // | APA | [7-4] | y | - // |--------------------------------------------------| - // | DPB | [3-0] | y | - // x--------------------------------------------------x - - // if instAttrReg1&(0xf<<28) != 0 { - // fmt.Println("GPI") - // } - f.setIf(instAttrReg1&(0xf<<28) != 24, GPA) - f.setIf(instAttrReg1&(0xf<<20) != 0, LRCPC) - f.setIf(instAttrReg1&(0xf<<16) != 0, FCMA) - f.setIf(instAttrReg1&(0xf<<12) != 0, JSCVT) - // if instAttrReg1&(0xf<<8) != 0 { - // fmt.Println("API") - // } - // if instAttrReg1&(0xf<<4) != 0 { - // fmt.Println("APA") - // } - f.setIf(instAttrReg1&(0xf<<0) != 0, DCPOP) - - // Store - c.featureSet.or(f) -} diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go deleted file mode 100644 index 574f9389c..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go +++ /dev/null @@ -1,17 +0,0 @@ -// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. - -//go:build (!amd64 && !386 && !arm64) || gccgo || noasm || appengine -// +build !amd64,!386,!arm64 gccgo noasm appengine - -package cpuid - -func initCPU() { - cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } - cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 } - xgetbv = func(uint32) (a, b uint32) { return 0, 0 } - rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 } - -} - -func addInfo(info *CPUInfo, safe bool) {} -func getVectorLength() (vl, pl uint64) { return 0, 0 } diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go deleted file mode 100644 index f924c9d83..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go +++ /dev/null @@ -1,41 +0,0 @@ -// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file. - -//go:build (386 && !gccgo && !noasm && !appengine) || (amd64 && !gccgo && !noasm && !appengine) -// +build 386,!gccgo,!noasm,!appengine amd64,!gccgo,!noasm,!appengine - -package cpuid - -func asmCpuid(op uint32) (eax, ebx, ecx, edx uint32) -func asmCpuidex(op, op2 uint32) (eax, ebx, ecx, edx uint32) -func asmXgetbv(index uint32) (eax, edx uint32) -func asmRdtscpAsm() (eax, ebx, ecx, edx uint32) -func asmDarwinHasAVX512() bool - -func initCPU() { - cpuid = asmCpuid - cpuidex = asmCpuidex - xgetbv = asmXgetbv - rdtscpAsm = asmRdtscpAsm - darwinHasAVX512 = asmDarwinHasAVX512 -} - -func addInfo(c *CPUInfo, safe bool) { - c.maxFunc = maxFunctionID() - c.maxExFunc = maxExtendedFunction() - c.BrandName = brandName() - c.CacheLine = cacheLine() - c.Family, c.Model, c.Stepping = familyModel() - c.featureSet = support() - c.SGX = hasSGX(c.featureSet.inSet(SGX), c.featureSet.inSet(SGXLC)) - c.AMDMemEncryption = hasAMDMemEncryption(c.featureSet.inSet(SME) || c.featureSet.inSet(SEV)) - c.ThreadsPerCore = threadsPerCore() - c.LogicalCores = logicalCores() - c.PhysicalCores = physicalCores() - c.VendorID, c.VendorString = vendorID() - c.HypervisorVendorID, c.HypervisorVendorString = hypervisorVendorID() - c.AVX10Level = c.supportAVX10() - c.cacheSize() - c.frequencies() -} - -func getVectorLength() (vl, pl uint64) { return 0, 0 } diff --git a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go deleted file mode 100644 index e7f874a7e..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go +++ /dev/null @@ -1,291 +0,0 @@ -// Code generated by "stringer -type=FeatureID,Vendor"; DO NOT EDIT. - -package cpuid - -import "strconv" - -func _() { - // An "invalid array index" compiler error signifies that the constant values have changed. - // Re-run the stringer command to generate them again. - var x [1]struct{} - _ = x[ADX-1] - _ = x[AESNI-2] - _ = x[AMD3DNOW-3] - _ = x[AMD3DNOWEXT-4] - _ = x[AMXBF16-5] - _ = x[AMXFP16-6] - _ = x[AMXINT8-7] - _ = x[AMXFP8-8] - _ = x[AMXTILE-9] - _ = x[APX_F-10] - _ = x[AVX-11] - _ = x[AVX10-12] - _ = x[AVX10_128-13] - _ = x[AVX10_256-14] - _ = x[AVX10_512-15] - _ = x[AVX2-16] - _ = x[AVX512BF16-17] - _ = x[AVX512BITALG-18] - _ = x[AVX512BW-19] - _ = x[AVX512CD-20] - _ = x[AVX512DQ-21] - _ = x[AVX512ER-22] - _ = x[AVX512F-23] - _ = x[AVX512FP16-24] - _ = x[AVX512IFMA-25] - _ = x[AVX512PF-26] - _ = x[AVX512VBMI-27] - _ = x[AVX512VBMI2-28] - _ = x[AVX512VL-29] - _ = x[AVX512VNNI-30] - _ = x[AVX512VP2INTERSECT-31] - _ = x[AVX512VPOPCNTDQ-32] - _ = x[AVXIFMA-33] - _ = x[AVXNECONVERT-34] - _ = x[AVXSLOW-35] - _ = x[AVXVNNI-36] - _ = x[AVXVNNIINT8-37] - _ = x[AVXVNNIINT16-38] - _ = x[BHI_CTRL-39] - _ = x[BMI1-40] - _ = x[BMI2-41] - _ = x[CETIBT-42] - _ = x[CETSS-43] - _ = x[CLDEMOTE-44] - _ = x[CLMUL-45] - _ = x[CLZERO-46] - _ = x[CMOV-47] - _ = x[CMPCCXADD-48] - _ = x[CMPSB_SCADBS_SHORT-49] - _ = x[CMPXCHG8-50] - _ = x[CPBOOST-51] - _ = x[CPPC-52] - _ = x[CX16-53] - _ = x[EFER_LMSLE_UNS-54] - _ = x[ENQCMD-55] - _ = x[ERMS-56] - _ = x[F16C-57] - _ = x[FLUSH_L1D-58] - _ = x[FMA3-59] - _ = x[FMA4-60] - _ = x[FP128-61] - _ = x[FP256-62] - _ = x[FSRM-63] - _ = x[FXSR-64] - _ = x[FXSROPT-65] - _ = x[GFNI-66] - _ = x[HLE-67] - _ = x[HRESET-68] - _ = x[HTT-69] - _ = x[HWA-70] - _ = x[HYBRID_CPU-71] - _ = x[HYPERVISOR-72] - _ = x[IA32_ARCH_CAP-73] - _ = x[IA32_CORE_CAP-74] - _ = x[IBPB-75] - _ = x[IBPB_BRTYPE-76] - _ = x[IBRS-77] - _ = x[IBRS_PREFERRED-78] - _ = x[IBRS_PROVIDES_SMP-79] - _ = x[IBS-80] - _ = x[IBSBRNTRGT-81] - _ = x[IBSFETCHSAM-82] - _ = x[IBSFFV-83] - _ = x[IBSOPCNT-84] - _ = x[IBSOPCNTEXT-85] - _ = x[IBSOPSAM-86] - _ = x[IBSRDWROPCNT-87] - _ = x[IBSRIPINVALIDCHK-88] - _ = x[IBS_FETCH_CTLX-89] - _ = x[IBS_OPDATA4-90] - _ = x[IBS_OPFUSE-91] - _ = x[IBS_PREVENTHOST-92] - _ = x[IBS_ZEN4-93] - _ = x[IDPRED_CTRL-94] - _ = x[INT_WBINVD-95] - _ = x[INVLPGB-96] - _ = x[KEYLOCKER-97] - _ = x[KEYLOCKERW-98] - _ = x[LAHF-99] - _ = x[LAM-100] - _ = x[LBRVIRT-101] - _ = x[LZCNT-102] - _ = x[MCAOVERFLOW-103] - _ = x[MCDT_NO-104] - _ = x[MCOMMIT-105] - _ = x[MD_CLEAR-106] - _ = x[MMX-107] - _ = x[MMXEXT-108] - _ = x[MOVBE-109] - _ = x[MOVDIR64B-110] - _ = x[MOVDIRI-111] - _ = x[MOVSB_ZL-112] - _ = x[MOVU-113] - _ = x[MPX-114] - _ = x[MSRIRC-115] - _ = x[MSRLIST-116] - _ = x[MSR_PAGEFLUSH-117] - _ = x[NRIPS-118] - _ = x[NX-119] - _ = x[OSXSAVE-120] - _ = x[PCONFIG-121] - _ = x[POPCNT-122] - _ = x[PPIN-123] - _ = x[PREFETCHI-124] - _ = x[PSFD-125] - _ = x[RDPRU-126] - _ = x[RDRAND-127] - _ = x[RDSEED-128] - _ = x[RDTSCP-129] - _ = x[RRSBA_CTRL-130] - _ = x[RTM-131] - _ = x[RTM_ALWAYS_ABORT-132] - _ = x[SBPB-133] - _ = x[SERIALIZE-134] - _ = x[SEV-135] - _ = x[SEV_64BIT-136] - _ = x[SEV_ALTERNATIVE-137] - _ = x[SEV_DEBUGSWAP-138] - _ = x[SEV_ES-139] - _ = x[SEV_RESTRICTED-140] - _ = x[SEV_SNP-141] - _ = x[SGX-142] - _ = x[SGXLC-143] - _ = x[SHA-144] - _ = x[SME-145] - _ = x[SME_COHERENT-146] - _ = x[SPEC_CTRL_SSBD-147] - _ = x[SRBDS_CTRL-148] - _ = x[SRSO_MSR_FIX-149] - _ = x[SRSO_NO-150] - _ = x[SRSO_USER_KERNEL_NO-151] - _ = x[SSE-152] - _ = x[SSE2-153] - _ = x[SSE3-154] - _ = x[SSE4-155] - _ = x[SSE42-156] - _ = x[SSE4A-157] - _ = x[SSSE3-158] - _ = x[STIBP-159] - _ = x[STIBP_ALWAYSON-160] - _ = x[STOSB_SHORT-161] - _ = x[SUCCOR-162] - _ = x[SVM-163] - _ = x[SVMDA-164] - _ = x[SVMFBASID-165] - _ = x[SVML-166] - _ = x[SVMNP-167] - _ = x[SVMPF-168] - _ = x[SVMPFT-169] - _ = x[SYSCALL-170] - _ = x[SYSEE-171] - _ = x[TBM-172] - _ = x[TDX_GUEST-173] - _ = x[TLB_FLUSH_NESTED-174] - _ = x[TME-175] - _ = x[TOPEXT-176] - _ = x[TSCRATEMSR-177] - _ = x[TSXLDTRK-178] - _ = x[VAES-179] - _ = x[VMCBCLEAN-180] - _ = x[VMPL-181] - _ = x[VMSA_REGPROT-182] - _ = x[VMX-183] - _ = x[VPCLMULQDQ-184] - _ = x[VTE-185] - _ = x[WAITPKG-186] - _ = x[WBNOINVD-187] - _ = x[WRMSRNS-188] - _ = x[X87-189] - _ = x[XGETBV1-190] - _ = x[XOP-191] - _ = x[XSAVE-192] - _ = x[XSAVEC-193] - _ = x[XSAVEOPT-194] - _ = x[XSAVES-195] - _ = x[AESARM-196] - _ = x[ARMCPUID-197] - _ = x[ASIMD-198] - _ = x[ASIMDDP-199] - _ = x[ASIMDHP-200] - _ = x[ASIMDRDM-201] - _ = x[ATOMICS-202] - _ = x[CRC32-203] - _ = x[DCPOP-204] - _ = x[EVTSTRM-205] - _ = x[FCMA-206] - _ = x[FP-207] - _ = x[FPHP-208] - _ = x[GPA-209] - _ = x[JSCVT-210] - _ = x[LRCPC-211] - _ = x[PMULL-212] - _ = x[SHA1-213] - _ = x[SHA2-214] - _ = x[SHA3-215] - _ = x[SHA512-216] - _ = x[SM3-217] - _ = x[SM4-218] - _ = x[SVE-219] - _ = x[lastID-220] - _ = x[firstID-0] -} - -const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXFP8AMXTILEAPX_FAVXAVX10AVX10_128AVX10_256AVX10_512AVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8AVXVNNIINT16BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBPB_BRTYPEIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBKEYLOCKERKEYLOCKERWLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSBPBSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSPEC_CTRL_SSBDSRBDS_CTRLSRSO_MSR_FIXSRSO_NOSRSO_USER_KERNEL_NOSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID" - -var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 61, 68, 73, 76, 81, 90, 99, 108, 112, 122, 134, 142, 150, 158, 166, 173, 183, 193, 201, 211, 222, 230, 240, 258, 273, 280, 292, 299, 306, 317, 329, 337, 341, 345, 351, 356, 364, 369, 375, 379, 388, 406, 414, 421, 425, 429, 443, 449, 453, 457, 466, 470, 474, 479, 484, 488, 492, 499, 503, 506, 512, 515, 518, 528, 538, 551, 564, 568, 579, 583, 597, 614, 617, 627, 638, 644, 652, 663, 671, 683, 699, 713, 724, 734, 749, 757, 768, 778, 785, 794, 804, 808, 811, 818, 823, 834, 841, 848, 856, 859, 865, 870, 879, 886, 894, 898, 901, 907, 914, 927, 932, 934, 941, 948, 954, 958, 967, 971, 976, 982, 988, 994, 1004, 1007, 1023, 1027, 1036, 1039, 1048, 1063, 1076, 1082, 1096, 1103, 1106, 1111, 1114, 1117, 1129, 1143, 1153, 1165, 1172, 1191, 1194, 1198, 1202, 1206, 1211, 1216, 1221, 1226, 1240, 1251, 1257, 1260, 1265, 1274, 1278, 1283, 1288, 1294, 1301, 1306, 1309, 1318, 1334, 1337, 1343, 1353, 1361, 1365, 1374, 1378, 1390, 1393, 1403, 1406, 1413, 1421, 1428, 1431, 1438, 1441, 1446, 1452, 1460, 1466, 1472, 1480, 1485, 1492, 1499, 1507, 1514, 1519, 1524, 1531, 1535, 1537, 1541, 1544, 1549, 1554, 1559, 1563, 1567, 1571, 1577, 1580, 1583, 1586, 1592} - -func (i FeatureID) String() string { - if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) { - return "FeatureID(" + strconv.FormatInt(int64(i), 10) + ")" - } - return _FeatureID_name[_FeatureID_index[i]:_FeatureID_index[i+1]] -} -func _() { - // An "invalid array index" compiler error signifies that the constant values have changed. - // Re-run the stringer command to generate them again. - var x [1]struct{} - _ = x[VendorUnknown-0] - _ = x[Intel-1] - _ = x[AMD-2] - _ = x[VIA-3] - _ = x[Transmeta-4] - _ = x[NSC-5] - _ = x[KVM-6] - _ = x[MSVM-7] - _ = x[VMware-8] - _ = x[XenHVM-9] - _ = x[Bhyve-10] - _ = x[Hygon-11] - _ = x[SiS-12] - _ = x[RDC-13] - _ = x[Ampere-14] - _ = x[ARM-15] - _ = x[Broadcom-16] - _ = x[Cavium-17] - _ = x[DEC-18] - _ = x[Fujitsu-19] - _ = x[Infineon-20] - _ = x[Motorola-21] - _ = x[NVIDIA-22] - _ = x[AMCC-23] - _ = x[Qualcomm-24] - _ = x[Marvell-25] - _ = x[QEMU-26] - _ = x[QNX-27] - _ = x[ACRN-28] - _ = x[SRE-29] - _ = x[Apple-30] - _ = x[lastVendor-31] -} - -const _Vendor_name = "VendorUnknownIntelAMDVIATransmetaNSCKVMMSVMVMwareXenHVMBhyveHygonSiSRDCAmpereARMBroadcomCaviumDECFujitsuInfineonMotorolaNVIDIAAMCCQualcommMarvellQEMUQNXACRNSREApplelastVendor" - -var _Vendor_index = [...]uint8{0, 13, 18, 21, 24, 33, 36, 39, 43, 49, 55, 60, 65, 68, 71, 77, 80, 88, 94, 97, 104, 112, 120, 126, 130, 138, 145, 149, 152, 156, 159, 164, 174} - -func (i Vendor) String() string { - if i < 0 || i >= Vendor(len(_Vendor_index)-1) { - return "Vendor(" + strconv.FormatInt(int64(i), 10) + ")" - } - return _Vendor_name[_Vendor_index[i]:_Vendor_index[i+1]] -} diff --git a/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go deleted file mode 100644 index 84b1acd21..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go +++ /dev/null @@ -1,121 +0,0 @@ -// Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file. - -package cpuid - -import ( - "runtime" - "strings" - - "golang.org/x/sys/unix" -) - -func detectOS(c *CPUInfo) bool { - if runtime.GOOS != "ios" { - tryToFillCPUInfoFomSysctl(c) - } - // There are no hw.optional sysctl values for the below features on Mac OS 11.0 - // to detect their supported state dynamically. Assume the CPU features that - // Apple Silicon M1 supports to be available as a minimal set of features - // to all Go programs running on darwin/arm64. - // TODO: Add more if we know them. - c.featureSet.setIf(runtime.GOOS != "ios", AESARM, PMULL, SHA1, SHA2) - - return true -} - -func sysctlGetBool(name string) bool { - value, err := unix.SysctlUint32(name) - if err != nil { - return false - } - return value != 0 -} - -func sysctlGetString(name string) string { - value, err := unix.Sysctl(name) - if err != nil { - return "" - } - return value -} - -func sysctlGetInt(unknown int, names ...string) int { - for _, name := range names { - value, err := unix.SysctlUint32(name) - if err != nil { - continue - } - if value != 0 { - return int(value) - } - } - return unknown -} - -func sysctlGetInt64(unknown int, names ...string) int { - for _, name := range names { - value64, err := unix.SysctlUint64(name) - if err != nil { - continue - } - if int(value64) != unknown { - return int(value64) - } - } - return unknown -} - -func setFeature(c *CPUInfo, name string, feature FeatureID) { - c.featureSet.setIf(sysctlGetBool(name), feature) -} -func tryToFillCPUInfoFomSysctl(c *CPUInfo) { - c.BrandName = sysctlGetString("machdep.cpu.brand_string") - - if len(c.BrandName) != 0 { - c.VendorString = strings.Fields(c.BrandName)[0] - } - - c.PhysicalCores = sysctlGetInt(runtime.NumCPU(), "hw.physicalcpu") - c.ThreadsPerCore = sysctlGetInt(1, "machdep.cpu.thread_count", "kern.num_threads") / - sysctlGetInt(1, "hw.physicalcpu") - c.LogicalCores = sysctlGetInt(runtime.NumCPU(), "machdep.cpu.core_count") - c.Family = sysctlGetInt(0, "machdep.cpu.family", "hw.cpufamily") - c.Model = sysctlGetInt(0, "machdep.cpu.model") - c.CacheLine = sysctlGetInt64(0, "hw.cachelinesize") - c.Cache.L1I = sysctlGetInt64(-1, "hw.l1icachesize") - c.Cache.L1D = sysctlGetInt64(-1, "hw.l1dcachesize") - c.Cache.L2 = sysctlGetInt64(-1, "hw.l2cachesize") - c.Cache.L3 = sysctlGetInt64(-1, "hw.l3cachesize") - - // from https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile - setFeature(c, "hw.optional.arm.FEAT_AES", AESARM) - setFeature(c, "hw.optional.AdvSIMD", ASIMD) - setFeature(c, "hw.optional.arm.FEAT_DotProd", ASIMDDP) - setFeature(c, "hw.optional.arm.FEAT_RDM", ASIMDRDM) - setFeature(c, "hw.optional.FEAT_CRC32", CRC32) - setFeature(c, "hw.optional.arm.FEAT_DPB", DCPOP) - // setFeature(c, "", EVTSTRM) - setFeature(c, "hw.optional.arm.FEAT_FCMA", FCMA) - setFeature(c, "hw.optional.arm.FEAT_FP", FP) - setFeature(c, "hw.optional.arm.FEAT_FP16", FPHP) - setFeature(c, "hw.optional.arm.FEAT_PAuth", GPA) - setFeature(c, "hw.optional.arm.FEAT_JSCVT", JSCVT) - setFeature(c, "hw.optional.arm.FEAT_LRCPC", LRCPC) - setFeature(c, "hw.optional.arm.FEAT_PMULL", PMULL) - setFeature(c, "hw.optional.arm.FEAT_SHA1", SHA1) - setFeature(c, "hw.optional.arm.FEAT_SHA256", SHA2) - setFeature(c, "hw.optional.arm.FEAT_SHA3", SHA3) - setFeature(c, "hw.optional.arm.FEAT_SHA512", SHA512) - // setFeature(c, "", SM3) - // setFeature(c, "", SM4) - setFeature(c, "hw.optional.arm.FEAT_SVE", SVE) - - // from empirical observation - setFeature(c, "hw.optional.AdvSIMD_HPFPCvt", ASIMDHP) - setFeature(c, "hw.optional.armv8_1_atomics", ATOMICS) - setFeature(c, "hw.optional.floatingpoint", FP) - setFeature(c, "hw.optional.armv8_2_sha3", SHA3) - setFeature(c, "hw.optional.armv8_2_sha512", SHA512) - setFeature(c, "hw.optional.armv8_3_compnum", FCMA) - setFeature(c, "hw.optional.armv8_crc32", CRC32) -} diff --git a/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go deleted file mode 100644 index ee278b9e4..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go +++ /dev/null @@ -1,130 +0,0 @@ -// Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file. - -// Copyright 2018 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file located -// here https://github.com/golang/sys/blob/master/LICENSE - -package cpuid - -import ( - "encoding/binary" - "io/ioutil" - "runtime" -) - -// HWCAP bits. -const ( - hwcap_FP = 1 << 0 - hwcap_ASIMD = 1 << 1 - hwcap_EVTSTRM = 1 << 2 - hwcap_AES = 1 << 3 - hwcap_PMULL = 1 << 4 - hwcap_SHA1 = 1 << 5 - hwcap_SHA2 = 1 << 6 - hwcap_CRC32 = 1 << 7 - hwcap_ATOMICS = 1 << 8 - hwcap_FPHP = 1 << 9 - hwcap_ASIMDHP = 1 << 10 - hwcap_CPUID = 1 << 11 - hwcap_ASIMDRDM = 1 << 12 - hwcap_JSCVT = 1 << 13 - hwcap_FCMA = 1 << 14 - hwcap_LRCPC = 1 << 15 - hwcap_DCPOP = 1 << 16 - hwcap_SHA3 = 1 << 17 - hwcap_SM3 = 1 << 18 - hwcap_SM4 = 1 << 19 - hwcap_ASIMDDP = 1 << 20 - hwcap_SHA512 = 1 << 21 - hwcap_SVE = 1 << 22 - hwcap_ASIMDFHM = 1 << 23 -) - -func detectOS(c *CPUInfo) bool { - // For now assuming no hyperthreading is reasonable. - c.LogicalCores = runtime.NumCPU() - c.PhysicalCores = c.LogicalCores - c.ThreadsPerCore = 1 - if hwcap == 0 { - // We did not get values from the runtime. - // Try reading /proc/self/auxv - - // From https://github.com/golang/sys - const ( - _AT_HWCAP = 16 - _AT_HWCAP2 = 26 - - uintSize = int(32 << (^uint(0) >> 63)) - ) - - buf, err := ioutil.ReadFile("/proc/self/auxv") - if err != nil { - // e.g. on android /proc/self/auxv is not accessible, so silently - // ignore the error and leave Initialized = false. On some - // architectures (e.g. arm64) doinit() implements a fallback - // readout and will set Initialized = true again. - return false - } - bo := binary.LittleEndian - for len(buf) >= 2*(uintSize/8) { - var tag, val uint - switch uintSize { - case 32: - tag = uint(bo.Uint32(buf[0:])) - val = uint(bo.Uint32(buf[4:])) - buf = buf[8:] - case 64: - tag = uint(bo.Uint64(buf[0:])) - val = uint(bo.Uint64(buf[8:])) - buf = buf[16:] - } - switch tag { - case _AT_HWCAP: - hwcap = val - case _AT_HWCAP2: - // Not used - } - } - if hwcap == 0 { - return false - } - } - - // HWCap was populated by the runtime from the auxiliary vector. - // Use HWCap information since reading aarch64 system registers - // is not supported in user space on older linux kernels. - c.featureSet.setIf(isSet(hwcap, hwcap_AES), AESARM) - c.featureSet.setIf(isSet(hwcap, hwcap_ASIMD), ASIMD) - c.featureSet.setIf(isSet(hwcap, hwcap_ASIMDDP), ASIMDDP) - c.featureSet.setIf(isSet(hwcap, hwcap_ASIMDHP), ASIMDHP) - c.featureSet.setIf(isSet(hwcap, hwcap_ASIMDRDM), ASIMDRDM) - c.featureSet.setIf(isSet(hwcap, hwcap_CPUID), ARMCPUID) - c.featureSet.setIf(isSet(hwcap, hwcap_CRC32), CRC32) - c.featureSet.setIf(isSet(hwcap, hwcap_DCPOP), DCPOP) - c.featureSet.setIf(isSet(hwcap, hwcap_EVTSTRM), EVTSTRM) - c.featureSet.setIf(isSet(hwcap, hwcap_FCMA), FCMA) - c.featureSet.setIf(isSet(hwcap, hwcap_FP), FP) - c.featureSet.setIf(isSet(hwcap, hwcap_FPHP), FPHP) - c.featureSet.setIf(isSet(hwcap, hwcap_JSCVT), JSCVT) - c.featureSet.setIf(isSet(hwcap, hwcap_LRCPC), LRCPC) - c.featureSet.setIf(isSet(hwcap, hwcap_PMULL), PMULL) - c.featureSet.setIf(isSet(hwcap, hwcap_SHA1), SHA1) - c.featureSet.setIf(isSet(hwcap, hwcap_SHA2), SHA2) - c.featureSet.setIf(isSet(hwcap, hwcap_SHA3), SHA3) - c.featureSet.setIf(isSet(hwcap, hwcap_SHA512), SHA512) - c.featureSet.setIf(isSet(hwcap, hwcap_SM3), SM3) - c.featureSet.setIf(isSet(hwcap, hwcap_SM4), SM4) - c.featureSet.setIf(isSet(hwcap, hwcap_SVE), SVE) - - // The Samsung S9+ kernel reports support for atomics, but not all cores - // actually support them, resulting in SIGILL. See issue #28431. - // TODO(elias.naur): Only disable the optimization on bad chipsets on android. - c.featureSet.setIf(isSet(hwcap, hwcap_ATOMICS) && runtime.GOOS != "android", ATOMICS) - - return true -} - -func isSet(hwc uint, value uint) bool { - return hwc&value != 0 -} diff --git a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go deleted file mode 100644 index 8733ba343..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go +++ /dev/null @@ -1,16 +0,0 @@ -// Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file. - -//go:build arm64 && !linux && !darwin -// +build arm64,!linux,!darwin - -package cpuid - -import "runtime" - -func detectOS(c *CPUInfo) bool { - c.PhysicalCores = runtime.NumCPU() - // For now assuming 1 thread per core... - c.ThreadsPerCore = 1 - c.LogicalCores = c.PhysicalCores - return false -} diff --git a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go deleted file mode 100644 index f8f201b5f..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go +++ /dev/null @@ -1,8 +0,0 @@ -// Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file. - -//go:build nounsafe -// +build nounsafe - -package cpuid - -var hwcap uint diff --git a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go deleted file mode 100644 index 92af622eb..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go +++ /dev/null @@ -1,11 +0,0 @@ -// Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file. - -//go:build !nounsafe -// +build !nounsafe - -package cpuid - -import _ "unsafe" // needed for go:linkname - -//go:linkname hwcap internal/cpu.HWCap -var hwcap uint diff --git a/vendor/github.com/klauspost/cpuid/v2/test-architectures.sh b/vendor/github.com/klauspost/cpuid/v2/test-architectures.sh deleted file mode 100644 index 471d986d2..000000000 --- a/vendor/github.com/klauspost/cpuid/v2/test-architectures.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -set -e - -go tool dist list | while IFS=/ read os arch; do - echo "Checking $os/$arch..." - echo " normal" - GOARCH=$arch GOOS=$os go build -o /dev/null . - echo " noasm" - GOARCH=$arch GOOS=$os go build -tags noasm -o /dev/null . - echo " appengine" - GOARCH=$arch GOOS=$os go build -tags appengine -o /dev/null . - echo " noasm,appengine" - GOARCH=$arch GOOS=$os go build -tags 'appengine noasm' -o /dev/null . -done |